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ST52T430/E430
(R)
ST52T430/E430
PRELIMINARY DATASHEET
8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, SCI
Memories Up to 8 Kbytes EPROM/OTP 256 bytes of RAM Readout Protection Core Register File Based Architecture 55 instructions Hardware multiplication and division Decision Processor for the implementation of Fuzzy Logic algorithms Clock and Power Supply Up to 20 MHz clock frequency. Power Saving features Interrupts 6 interrupt vectors Top Level External Interrupt (INT) Peripherals 3 Programmable 8-bit Timer/PWMs with internal 16-bit Prescaler featuring: - PWM output - Input capture - Output Compare - Pulse Generator mode
I/O Ports
23 I/O PINs configurable in Input and Output
mode
High current sink/source in all pins.
Development tools High level Software tools Emulator Low cost Programmer Gang Programmer
Watchdog timer On-chip 8-bit Sample and Hold A/D Converter
with 8-channel analog multiplexer asynchronous protocol (UART)
Serial Communication Interface with
ST52X430 Devices Summary
Device NVM RAM Timer PWM 3x8-bit 3x8-bit 3x8-bit 3x8-bit ADC SCI Watchdog Operating Supply 3.0-5.5 V 3.0-5.5 V 3.0-5.5 V 3.0-5.5 V I/O Package
ST52T430K1 ST52T430K2 ST52T430K3 ST52E430K3
2K OTP 4K OTP 8K OTP 8K EPROM
256 256 256 256
8-Ch 8-Ch 8-Ch 8-Ch
Yes Yes Yes Yes
Yes Yes Yes Yes
23 23 23 23
Sdip32 Sso34 Tqfp32 Sdip32 Sso34 Tqfp32 Sdip32 Sso34 Tqfp32 Csdip32w
Rev. 1.9 - May 2003 1/88 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
ST52T430/E430
2/88
ST52T430/E430
TABLE TENTS OF CON-
TABLE OF CONTENTS
. . . . . .7 . . . . . .7 ..... 7 ..... 8 . . . . .12
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Memory Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 INTERNAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 ST52X430 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.2 Control Unit and Data Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.2.1 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.3.1 RAM and STACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.2 Input Registers Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.4 Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4 Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 EPROM Programming Phase Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.1.1 EPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.2 EPROM Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.3 EPROM Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.4 EPROM Read/Verify Margin Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.5 Stand by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.6 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 Eprom Erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.2 Global Interrupt Request Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.4 Interrupt Maskability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.5 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.6 Interrupts and Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 4.7 Interrupt RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5 CLOCK, RESET & POWER SAVING MODE. . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.3 Power Saving Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.3.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6.2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6.3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 6.4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 6.5 I/O Port Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7 FUZZY COMPUTATION (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1 Fuzzy Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 7.2 Fuzzyfication Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 7.3 Inference Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 7.4 Defuzzyfication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 7.5 Input Membership Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 7.6 Output Singleton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 7.7 Fuzzy Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
8 A/D CONVERTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 8.2 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 8.2.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2.2 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.3 A/D Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
9 WATCHDOG TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.1 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 9.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
10 PWM/TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1 Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 10.2 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 10.3 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
11 SERIAL COMMUNICATION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.1 SCI Receiver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 11.2 SCI Transmitter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 11.3 Baud Rate Generator Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.1 Parameter Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 12.3 Recommended Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 12.4 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
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12.5 Clock and Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 12.6 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 12.7 ESD Pin Protection Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 12.7.1 Standard Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.7.2 Multi-supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.8 Port Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.9 Control Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 12.9.1 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.9.2 VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.10 8-bit A/D Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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1 GENERAL DESCRIPTION 1.1 Introduction ST52X430 is an 8-bit Intelligent Control Units (ICU) of the ST Five Family, which can perform both boolean and fuzzy algorithms in an efficient manner, in order to reach the best performances that the two methodologies allow. ST52X430 is produced by STMicroelectronics using the reliab le hig h performance CMO S process, including integrated-on-chip peripherals that allow maximization of system reliability, decreasing system costs and minimizing the number of external components. The flexible I/O configuration of ST52x400/440 allows for an interface with a wide range of external devices, like D/A converters or power control devices. ST52X430 pins are configurable, allowing the user to set the input or output signals on each single pin. A hardware multiplier (8 bit by 8 bit with 16 bit result) and a divider (16 bit over 8 bit with 8 bit result and 8 bit remainder) are available to implement complex functions by using a single instruction. The program memory utilization and computational speed is optimized. Fuzzy Logic dedicated structures in ST52X430 ICU's can be exploited to model complex systems with high accuracy in a useful and easy way. Fu z z y E x p e r t S y s t e m s f o r o v e r a ll s y s te m management and fuzzy Real time Controls can be designed to increase performances at highly competitive costs. The linguistic approach characterizing Fuzzy Logic is based on a set of IF-THEN rules, which describe the control behavior, as well as on Membership Functions, which are associated to input and output variables. Up to 334 Membership Functions, with triangular and trapezoidal shapes, or singleton values are available to describe fuzzy variables. Th e Timer /PW M pe riph era l allo ws the management of power devices and timing signals, implementing different operating modes and high frequency PWM (Pulse With Modulation) controls. Input Capture and Output Compare functions are available on the TIMER. The programmable Timer has a 16 bit Internal Prescaler and an 8 bit Counter. It can use internal or external Start/Stop signals and clock. An internal programmable Watchdog is available to avoid loop errors and to reset the ICU. ST52X430 includes an 8-bit Analog to Digital Converter with an 8-analog channel Multiplexer. Single/Multiple channels and Single/Sequence conversion modes are supported. A Serial Communication peripheral (SCI), which uses the UART protocol allows data transfer from the ST52X430 to other external devices. In order to optimize energy consumption, two different power saving modes are available: Wait mode and Halt mode. Program Memory (EPROM/OTP) addressing capability addresses up to 8 Kbytes of memory locations to store both program instructions and permanent data. EPROM can be locked by the user to prevent external undesired operations. Operations may be performed on data stored in RAM, allowing the direct combination of new input and feedback data. All bytes of RAM are used like Register File. OTP (One Time Programmable) version devices are fully compatible with the EPROM windowed version, which may be used for prototyping and pre-production phases of development. A powerful development environment consisting of a b oard a nd software too ls allow s a n easy configuration and use of ST52X430. T h e VI S U A L FI V E T M s o f tw a r e t o o l a l lo w s development of projects through a user-friendly graphical interface and optimization of generated code. 1.2 Functional Description ST52X430 ICU can work in two modes: s Memory Programming Mode
s
Working Mode
according to RESET and Vpp signals levels (see pins description). Note: When RESET=0 it is advisable not to use the sequence "101010" to port PA (7 : 2). 1.2.1 Memory Programming Mode. The ST52X430 memory is loaded in the Memory Programming Phase. All fuzzy and standard instructions are written inside the memory. This phase starts by setting the control signals as illustrated below:
RESET Vss
TEST
Vss
VPP
12V/VDD
When this phase starts, the ST52X430 core is set to RESET status; then 12V are applied to the Vpp
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pin in order to start EPROM programming. A signal applied to PB1 is used to increment the memory address; the data is supplied to PORT A (see EPROM programming for further details). 1.2.2 Working mode. Below are the control signals of this mode: RESET
VDD
TEST
VSS
VPP
VSS
The processor starts the working phase following the instructions, which have been previously loaded in the memory. S T 5 2 x 4 3 0 ' s i n t e r n a l s t r u c t u r e in c l u d e s a computational block, CONTROL UNIT (CU) / DATA PROCESSING UNIT (DPU), which allows pro ces sin g of b oo le an fu nction s an d fuzz y algorithms. Figure 1.1 TQFP32 Pin Configuration
The CU/DPU can manage up to 334 different M e mb e r sh ip Fu n c tio n s fo r th e f u zz y ru le s antecedent part. The rule consequents are "crisp" values (real numbers). The maximum number of r ules tha t ca n b e d e fin e d is lim ite d b y th e d im e n s io n s o f th e i m p le m e n t e d s t a n d a r d algorithm. EPR OM is th en sh are d be tw ee n fuzzy an d standard algorithms. The Membership Function data is stored inside the first 1024 memory locations. The Fuzzy rules are parts of the program instructions. The Control Unit (CU) reads the information and the status deriving from the peripherals. Arithmetic calculus can be performed on these values by using the internal CU and the 128/256 bytes of RAM, which supports all computations. The peripheral input can be fuzzy and/or arithmetic output, or the values contained in Data RAM and EPROM locations.
32 INT / PC0 T0OUT / PC1 T1OUT / PC2 T2OUT / PC3 TX / PC4 RX / PC5 PC6 PC7 1 2 3 4 5 6 7 8 9
31
30
29
28
27
26
25 24 23 22 21 20 19 18 17 PA1 / T0OUT PA2 / T1OUT PA3 / T2OUT PA4 / STRT PA5 / T0CLK PA6 PA7 / PB7 / AIN7 PB6 / AIN6
10
11
12
13
14
15
16
GNDA
AIN4 / PB4
AIN0 / PB0
AIN1 / PB1
AIN2 / PB2
8/88
AIN5 / PB5
AIN3 / PB3
Vdda
PA0 / T0RES
OSCOUT
RESET
OSCIN
TEST
Vdd
Vpp
Vss
ST52T430/E430
Figure 1.2 SSO34 Pin Configuration
RESET OSCOUT OSCIN TEST INT/PC0 T0OUT/PC1 T1OUT/PC2 T2OUT/PC3 TX/PC4 RX/PC5 PC6 PC7 nc PB0/Ain0 PB1/Ain1 PB2/Ain2 PB3/Ain3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
VDD Vss VPP PA0/T0RES PA1/T0OUT PA2/T1OUT PA3/T2OUT PA4/T0STRT PA5/T0CLK PA6 PB7/PA7/Ain7 PB6/Ain6 nc PB5/Ain5 PB4/Ain4 GNDA VDDA
Figure 1.3 PSDIP32 Pin Configuration
RESET OSCOUT OSCIN TEST INT/PC0 T0OUT/PC1 T1OUT/PC2 T2OUT/PC3 TX/PC4 RX/PC5 PC6 PC7 PB0/Ain0 PB1/Ain1 PB2/Ain2 PB3/Ain3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD Vss VPP PA0/T0RES PA1/T0OUT PA2/T1OUT PA3/T2OUT PA4/T0STRT PA5/T0CLK PA6 PB7/PA7/Ain7 PB6/Ain6 PB5/Ain5 PB4/Ain4 GNDA VDDA
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Table 1.1 ST52X430 SSO34 & PSDIP32 Pin list
SSO34 Pins 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 21 22 23 24 25 26 27 28 29 30 31 32 13 14 15 16 17 18 19 20 SDIP32 Pins 1 2 3 4 5 6 7 8 9 10 11 12 NAME RESET OSCOUT OSCIN TEST INT/PC0 T0OUT/PC1 T1OUT/PC2 T2OUT/PC3 TX/PC4 RX/PC5 PC6 PC7 nc Ain0/PB0 Ain1/PB1 Ain2/PB2 Ain3/PB3 VDDA GNDA Ain4/PB4 Ain5/PB5 nc Ain6/PB6 Ain7/PB7/PA7 PA6 T0CLK/PA5 T0STRT/PA4 T2OUT/PA3 T1OUT/PA2 T0OUT/PA1 T0RES/PA0 VPP Vss VDD I/O EPROM Data I/O EPROM Data I/O EPROM Data I/O EPROM Data I/O EPROM Data I/O EPROM Data I/O EPROM Data I/O EPROM Data EPROM Programming Power supply (12V 5%) Digital Ground Digital Power Supply Analog Input, Digital I/O Analog Input, Digital I/O Digital I/O Timer/PWM 0 clock, Digital I/O Timer/PWM 0 start/stop, Digital I/O
Timer/PWM 2 compl. output, Digital I/O Timer/PWM 1 compl. output, Digital I/O Timer/PWM 0 compl. output, Digital I/O
Programming Phase General Reset
Working Phase General Reset Oscillator Output Oscillator Input
Must be tied to Vss PHASE signal (PHASE)
Must be tied to Vss External interrupt, Digital I/O Timer/PWM 0 output, Digital I/O Timer/PWM 1 output, Digital I/O Timer/PWM 2 output, Digital I/O SCI Output, Digital I/O SCI Input, Digital I/O Digital I/O Digital I/O
Address Reset (RST_ADD) Address Increment (INC_ADD) Configuration Reset (RST_CONF) Configuration Increment (INC_CONF) Analog Power Supply Analog Ground
Analog Input, Digital I/O Analog Input, Digital I/O Analog Input, Digital I/O Analog Input, Digital I/O Analog Power Supply Analog Ground Analog Input, Digital I/O Analog Input, Digital I/O
Timer/PWM 0 Reset, Digital I/O EPROM VDD or Vss Digital Ground Digital Power Supply
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Table 1.2 ST52X430 TQFP32 Pin list
TQFP32 Pins 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME INT/PC0 T0OUT/PC1 T1OUT/PC2 T2OUT/PC3 TX/PC4 RX/PC5 PC6 PC7 Ain0/PB0 Ain1/PB1 Ain2/PB2 Ain3/PB3 VDDA GNDA Ain4/PB4 Ain5/PB5 Ain6/PB6 Ain7/PB7/PA7 PA6 T0CLK/PA5 T0STRT/PA4 T2OUT/PA3 T1OUT/PA2 T0OUT/PA1 T0RES/PA0 VPP Vss VDD RESET OSCOUT OSCIN TEST Must be tied to Vss I/O EPROM Data I/O EPROM Data I/O EPROM Data I/O EPROM Data I/O EPROM Data I/O EPROM Data I/O EPROM Data I/O EPROM Data EPROM Programming Power supply (12V 5%) Digital Ground Digital Power Supply General Reset Address Reset (RST_ADD) Address Increment (INC_ADD) Configuration Reset (RST_CONF) Configuration Increment (INC_CONF) Analog Power Supply Analog Ground Programming Phase PHASE signal (PHASE) Working Phase External interrupt, Digital I/O Timer/PWM 0 output, Digital I/O Timer/PWM 1 output, Digital I/O Timer/PWM 2 output, Digital I/O SCI Output, Digital I/O SCI Input, Digital I/O Digital I/O Digital I/O Analog Input, Digital I/O Analog Input, Digital I/O Analog Input, Digital I/O Analog Input, Digital I/O Analog Power Supply Analog Ground Analog Input, Digital I/O Analog Input, Digital I/O Analog Input, Digital I/O Analog Input, Digital I/O Digital I/O Timer/PWM 0 clock, Digital I/O Timer/PWM 0 start/stop, Digital I/O Timer/PWM 2 compl. output, Digital I/O Timer/PWM 1 compl. output, Digital I/O Timer/PWM 0 compl. output, Digital I/O Timer/PWM 0 Reset, Digital I/O EPROM VDD or Vss Digital Ground Digital Power Supply General Reset Oscillator Output Oscillator Input Must be tied to Vss
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1.3 Pin Description V DD, V SS, VDDA, GNDA, V PP. In order to avoid noise disturbances, the power supply of the digital part is kept separate from the power supply of the analog part. VDD. Main Power Supply Voltage (5V 10%). VSS. Digital circuit ground. V DDA . An alog V DD o f the Ana lo g to Digital Converter. GNDA. Analog V SS of the Analog to Digital Converter. Must be tied to VSS. V PP. Main Power Supply for internal EPROM (12.5V5%, in programming phase) and MODE s e l e c t o r . D u r i n g t h e P r o g r a m m in g p h a s e (programming), V PP must be set at 12V. In the Working phase VPP must be equal to VSS. OSCin and OSCout. These pins are internally connected with the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the correct operations of ST52X430 with various stability/cost trade-off. An external clock signal can be applied to OSCin, in this case OSCout must be floating. RESET. This signal is used to restart ST52X430 at the beginning of its program. It also allows one to select the program mode for EPROM. Ain0-Ain8. These 8 lines are connected to the input of the analog multiplexer. They allow the a c q u i s it i o n o f 8 a n a lo g i n p u t . D u r i n g t h e Programming phase, Ain0, Ain1, Ain2 and Ain3 are used to manage EPROM operation. PA0-PA7, PB0-PB7, PC0-PC7. These lines are organized as I/O port. Each pin can be configured as input or output. PA7/PB7 are tied to the same output. During Programming phase PA port is used for EPROM read/write data. T0RES, T0CLK, T0STRT. These pins are related with the internal Programmable Timer/PWM 0. This Timer can be reset externally by using T0RES. In Working Mode, T0RES resets the address counter of the Timer. T0RES is active at low level. The Timer 0 Clock can be the internal clock or can be supplied externally by using pin T0CLK. An external Start/Stop signal can be used to control the Timer through T0STRT pin. T0OUT, T1OUT, T2OUT. The TIMER/PWM outputs are available on these pins. T0OUT, T1OUT, T2OUT. The TIMER/PWM complementary outputs are available on these pins. Tx. Serial data output of SCI transmitter block Rx. Serial data input of the SCI receiver block. TEST. During the Programming and Working phase it must be set to Vss.
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Figure 1.4 ST52X430 Block Diagram
TIMER/PWM 0 PROGRAM MEMORY EPROM TIMER/PWM 2 CORE
INTERRUPTS CONTROLLER ALU & DPU DECISION PROCESSOR CONTROL UNIT
Register File 256 bytes Input registers
TIMER/PWM 1
PA7:0
PORT A
PORT C
PC7:0
SCI
PORT B
PB7:0
VDDA
ADC
GNDA
PC FLAGS
WATCHDOG
POWER SUPPLY
OSCILLATOR
RESET CIRCUIT
VDD
VPP
VSS
OSCIN OSCOUT
RESET
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2 INTERNAL ARCHITECTURE ST52X430 is made up of the following blocks and peripherals: s Control Unit (CU) and Data Processing Unit (DPU)
s s s s s s s s
parts of the CU so that only one part of the system is activated during working mode. The CU structure is very flexible. It was designed with the purpose of easily adapting the core of the microcontroller to market needs. New instruction sets or new peripherals can be easily included without changing the structure of the microcontroller, maintaining code compatibility. The CU reads the instructions stored on EPROM (Fetch) and decodes them. According to the instruction types, the arbiter activates one of the main blocks of the CU. Afterwards, all the control signals for the DPU are generated. A set of 46 different arithmetic, fuzzy and logic instructions is available. Each instruction requires 6 (fuzzy instructions) to 26 (DIVISION) clock pulses to be performed. The DPU receives, stores and sends instructions deriving from EPROM, RAM or peripherals in order to execute them. 2.2.1 Program Counter. The Program Counter (PC) is a 13-bit register that contains the address of the next memory location to be processed by the core. This memory location may be an opcode, operand, or an address of an operand. The 13-bit length allows direct addressing of a maximum of 8,192 bytes in the program space. After having read the current instruction address, the PC value is incremented. The result of this operation is shifted back into the PC. The PC can be changed in the following ways:
s
ALU / Fuzzy Core EPROM 256 Byte RAM Clock Oscillator Analog Multiplexer and A/D Converter 3 PWM / Timers SCI Digital I/O port
2.1 ST52X430 Operating Modes ST52X430 works in two modes, Programming and Working Modes, depending on the control signals level RESET, TEST and VPP The Operating modes are selected by setting the control signal level as specified in the Control Signals Setting table.
Table 2.1 Control Signals Setting
Control Signal RESET TEST Programming VSS VSS Reset VSS VSS Working VDD VSS
JP (Jump)PC = Jump Address InterruptPC = Interrupt Vector RETIPC = Pop (stack) RETPC = Pop (stack) CALLPC = Subroutines address ResetPC = Reset Vector Normal InstructionPC = PC + 1
VPP
12 V
VSS
VSS
s s s s s
2.2 Control Unit and Data Processing Unit The Control Unit (CU) formally includes five main blocks. Each block decodes a set of instructions, generating the appropriate control signals. The main parts of the CU are illustrated in Figure 2.1. The five different parts of the CU manage Loading, Logic/Arithmetic, Jump, Control and the Fuzzy instruction set. The block called "Collector" manages the signals deriving from the different parts of the CU, defining the signals for the Data Processing Unit (DPU) and the different peripherals of the microcontroller. The block called "Arbiter" manages the different-
s
2.2.2 Flags. The ST52X430 core includes a different set of flags that correspond to 2 different modes: normal mode and interrupt mode. Each set of flags consists of a CARRY flag (C), ZERO flag (Z) and SIGN flag (S). One set (CN, ZN, SN) is used during normal operation and one is used during interrupt mode (CI, ZI, SI). Formally, the user has to manage only one set of flags: C, Z and S.
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Figure 2.1 Data Processing Unit (DPU)
CU
E PROM INPU T S PER IPH ERAL S
PR OGRAM COU NTER M U X
add_EP R
PER IPHER ALS
RAM ADD RE SS R AM STAC K POINT 256 Bytes FUZZY R EGIS TERS
M U LTIPLEXER
ACC UM U LATOR
FLAGS REG. ALU
Figure 2.2 CU/DPU Block Diagram
R A M D a t a 8 B it R A M A d d r. 8 B it RAM D a ta O u t 8 B it M ic r o c o d e
RAM E P R O M
C U
C o n t r o l S ig n a ls
D P U
T o P e r ip h e ra ls F ro m P e r ip h e r a ls
E P R O M A d d re s s
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The ST52X430 core uses flags that correspond to the actual mode. As soon as an interrupt is generated the ST52X430 core uses the interrupt flags instead of the normal flags. Each interrupt level has its own set of flags, which is saved in the STACK together with the Program Counter. These flags are restored from the STACK automatically when a RETI instruction is executed. If the MCU was in normal mode before an interrupt, the normal flags are restored when the RETI instruction is executed. Note: A CALL subroutine is a normal mode execution. For this reason, a RET instruction, consequent to a CALL instruction does not affect the normal mode set of flags. Flags are not cleared during context switching and remain in the state they were at the end of the last interrupt routine switching. The Carry flag is set when an overflow occurs during arithmetic operations, otherwise it is cleared. The Sign flag is set when an underflow occurs during arithmetic operations, otherwise it is cleared. 2.3 Address Spaces ST52X430 has four separate address spaces: s RAM: 256 Bytes Figure 2.3 Address Spaces Description
s s s s
Input Registers: 20 8-bit registers Output Registers 10 8-bit registers Configuration Registers: 21 8-bit registers
Program memory up to 8K Bytes Program memory will be described in further details in the MEMORY section 2.3.1 RAM and STACK. RAM memory consists of 256 general purpose 8bit RAM registers. All the registers in RAM can be specified by using a decimal address. For example, 0 identifies the first register of RAM. To read or write RAM registers LOAD instructions must be used. See Table 2.5 Each interrupt level has its own set of flags, which is saved in the STACK together with the Program Counter. These flags are restored from the STACK automatically when a RETI instruction is executed. When the instructions like Interrupt request or CALL are executed, a STACK level is used to push the PC. The STACK is located in RAM. For each level of stack, 2 bytes of RAM are used. The values of this stack are stored from the last RAM register (address 255). The maximum level of stack must be less than 128.
ST52X430 CORE
PROGRAM MEMORY
ON CHIP PERIPHERALS
PERIPHERAL REGISTERS INPUT REGISTERS LDPR CONTROL UNIT RAM DPU ALU PERIPHERAL CONFIGURATION REGISTERS BLOCK
LDRI LDRC LDCE LDCR
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The STACK POINTER indicates the first level available to store data. When a subroutine call or interrupt request occurs, the content of the PC and the current set of flags are stored into the level located by the STACK POINTER. When a interrupt return occurs (RETI instruction), the data stored in the highest stack level is restored back into the PC and current flags. Instead, when a subroutine return occurs (RET instruction) the data stored in the highest stack level are restored in the PC not affecting the flags. These operating modes are illustrated in Figure 2.4. Note: The user must pay close attention to avoid overwriting RAM locations where the STACK could be stored. 2.3.2 Input Registers Bench. The Input Registers (IR) bench consists of 20 8-bit registers containing data or the status of the peripherals. All the registers can be specified by using a decimal address (for example, 0 identifies the first register of the IR). The assembler instruction: LDRI RAM_Reg. IR_i loads the value of the i-th IR in the RAM location identified by the RAM_Reg address. The first input register is dedicated to store the value of the stack pointer. The next 8 registers (ADC_OUT_0:7) of the IR are dedicated to the 8 converted values deriving from the ADC. The last 9 Input Registers contain data from the I/O ports and PWM/Timers. The following table summarizes the IR address and the relative peripherals. In order to simplify the concept, a mnemonic name is assigned to the registers. The same name is used in VISUALSTUDIO(R) development tools
Figure 2.4 Stack Operation
PROGRAMCOUNTER
RAM
REG 0 REG 1 REG 2 REG 3 REG 4 REG 5
WHEN CALL OR INTERRUPT REQ. OCCURS
WHEN RETI OR RET OCCURS Stack Pointer
STACK LEVEL n .......................... REG 252 REG 253 REG 254 REG 255 STACK LEVEL 2 STACK LEVEL 1
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Table 2.2 Input Registers
IR MNEMONIC NAME STACK_POINTER CHAN 0 CHAN 1 CHAN 2 CHAN 3 CHAN 4 CHAN 5 CHAN 6 CHAN 7 PORT_A PORT_B PORT_C PWM_ 0_COUNT PWM_ 0_ STATUS PWM_ 1_ COUNT PWM_ 1_ STATUS PWM_ 2_ COUNT PWM_ 2_ STATUS SCI_RX SCI_STATUS PERIPHERAL REGISTER STACK POINTER A/D CHANNEL 0 A/D CHANNEL 1 A/D CHANNEL 2 A/D CHANNEL 3 A/D CHANNEL 4 A/D CHANNEL 5 A/D CHANNEL 6 A/D CHANNEL 7 PORT A INPUT REGISTER PORT B INPUT REGISTER PORT C INPUT REGISTER PWM/TIMER 0 COUNTER PWM/TIMER 0 STATUS REGISTER PWM/TIMER 1 COUNTER PWM/TIMER 1 STATUS REGISTER PWM/TIMER 2 COUNTER PWM/TIMER 2 STATUS REGISTER SCI DATA REGISTER SCI STATUS REGISTER ADDRESS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
2.3.3 Configuration Registers. The ST52X430 configuration Registers allow the configuration of all the blocks of the fuzzy microcontroller. Table 2.3 describes the functions and the related peripherals of each of the Configuration Registers. By using the load Table 2.3 Configuration Registers
CONFIGURATION REGISTER REG_CONF 0 REG_CONF 1 REG_CONF 2 REG_CONF 3
instructions, the Configuration Registers can be set by using values stored in the Program Memory (EPROM) or in RAM. Use and meaning of each register will be described in further details in the corresponding section.
PERIPHERAL INTERRUPT MASK N.U. WATCHDOG TIMER A/D CONVERTER
DESCRIPTION Interrupts mask setting N.U. Watchdog Timer Configuration A/D configuration
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Table 2.3 Configuration Registers (continued)
CONFIGURATION REGISTER REG_CONF 4 REG_CONF 5 PERIPHERAL PORT A PWM/TIMER 0 DESCRIPTION Set the relative bit like digital input or digital output PWM/Timer 0 Working mode Configuration PWM/TIMER 0 Prescaler configuration and output waveform selection. PWM/TIMER 0 Working Mode Configuration PWM/TIMER 1 Working Mode Configuration PWM/TIMER 1 Prescaler configuration and output waveform selection. PWM/TIMER 2 Working Mode Configuration PWM/Timer 2 Prescaler configuration and output waveform selection. Set the bit 0,1 and 2 like Digital I/O or complementary Timers Output. Set the relative bit like digital input or digital output. Set the relative I/O like Digital or Analog. Set the relative I/O like digital input or digital output Set the relative I/O like Digital I/O or Timers Output Set the Interrupts priority Set the Interrupts priority Set the SCI working mode Set the SCI working mode
REG_CONF 6
PWM/TIMER 0
REG_CONF 7 REG_CONF 8
PWM/TIMER 0 PWM/TIMER 1
REG_CONF 9
PWM/TIMER 1
REG_CONF 10
PWM/TIMER 2
REG_CONF 11
PWM/TIMER 2
REG_CONF 12 REG_CONF 13 REG_CONF 14 REG_CONF 15 REG_CONF 16 REG_CONF 17 REG_CONF 18 REG_CONF 19 REG_CONF 20
PORT A PORT B PORT B PORT C PORT C Interrupt Priority Interrupt Priority SCI SCI
2.3.4 Output Registers. The Output Registers (OR) consist of 10 registers containing data for the microcontroller peripherals including the I/O Ports. All registers can be specified by using a decimal address (for example, 1 identifies the second OR). By using LOAD instructions the Output Registers (OR) may be set by using values stored in the Program Memory (LDPE) or in RAM (LDPR) The assembler instruction: LDPR OR_i RAM_Reg.
loads the value of the RAM location identified by the address RAM_Reg in the OR i-th Table 2.4 describes OR. In order to simplify the concept, a mnemonic name is assigned to OR. The same names are used in FUZZYSTUDIOTM 4.0 development tools. Use and meaning of each register will be described in further details in the corresponding section.
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Table 2.4 Output Registers
OR MNEMONIC NAME PORT_ A PORT_ B PORT_C PWM_0_COUNT PWM_0_RELOAD PWM_1_COUNT PWM_1_RELOAD PWM_ 2_ COUNT PWM_2_RELOAD SCI_TX_DATA PERIPHERAL REGISTER PORT A OR PORT B OR PORT C OR TIMER/PWM 0 COUNTER TIMER/PWM 0 RELOAD REGISTER TIMER/PWM 1 COUNTER TIMER/PWM 1 RELOAD REGISTER TIMER/PWM 2 COUNTER TIMER/PWM 2 RELOAD REGISTER SCI DATA REGISTER ADDRESS 0 1 2 3 4 5 6 7 8 9
2.4 Arithmetic Logic Unit The 8-bit Arithmetic Logic Unit (ALU) allows the performance of arithmetic calculations and logic instructions, which can be divided into 5 groups: Load, Arithmetic, Jump, Interrupts and Program Control instructions (refer to the ST52X430 Assembler Set for further details). The computational time required for each instruction consists of one clock pulse for each Cycle plus 3 clock pulses for the decoding phase. Table 2.5 Load instructions
The ALU of the ST52X430 can perform multiplication (MULT) and division (DIV). Multiplication is performed by using 8 bit operands storing the result in 2 registers (16 bit values), see Figure 2.5 and Figure 2.6. WARNING: If the LSB of the multiplication result is 0, the Zero flag is set although the result is not 0.
Load Instructions Mnemonic LDCE LDCR LDFR LDPE LDPE LDPR LDRC LDRE LDRE LDRI LDRR Instruction LDCE conf, EPROM LDCR conf, RAM LDFR FUZZY_i_RAM RAM LDPE per, EPROM LDPE per, (RAM) LDPR reg, RAM LDRC RAM, const LDRE RAMi, EPROMi LDRE (RAMi), (RAMj) LDRI RAM, inp_reg LDRR RAMi, RAMj Bytes 3 3 3 3 3 3 3 3 3 3 3 Cycles 17 14 14 17 17 14 14 16 18 15 16 Z S C -
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Table 2.5 Load instructions
PGSET PGSET const 2 9 -
Table 2.6 Arithmetic & Logic instructions set
Arithmetic Instructions Mnemonic ADD ADDO AND ASL ASR DEC DIV INC MULT NOT OR SUB SUBO MIRROR Instruction ADD regi, regj ADDO regi, regj AND regi, regj ASL regi ASR regi DEC regi DIV regi, regj INC regi MULT regi, regj NOT regi OR regi, regj SUB regi, regj SUBO regi, regj MIRROR regi Bytes 3 3 3 2 2 2 3 2 3 2 3 3 3 2 Cycles 17 20 17 15 15 15 26 15 19 15 17 17 20 15 Z I I I I I I I I I I I I I I S I I I I I I C I I I I I I -
Table 2.7 Jump Instruction Set
Jump instructions mnemonic call jp jpc jpnc jpns jpnz jps jpz ret instruction call addr jp addr jpc addr jpnc addr jpns addr jpnz addr jps addr jpz addr ret bytes 3 3 3 3 3 3 3 3 1 cycles 18 12 10/12 10/12 10/12 10/12 10/12 10/12 13 z s c -
Table 2.8 Interrupt Instructions Set
Interrupt Instructions Mnemonic HALT MEGI Instruction HALT MEGI Bytes 1 1 Cycles 7/15 7/15 Z S C -
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Table 2.8 Interrupt Instructions Set (continued)
MDGI RETI RINT UDGI UEGI WAITI MDGI RETI RINT INT UDGI UEGI WAITI 1 1 2 1 1 1 6 12 8 6 7/15 7/14 -
Table 2.9 Control Instructions Set
Control Instructions Mnemonic FUZZY NOP WDTRFR WDTSLP Instruction FUZZY NOP WDTRFR WDTSLP Bytes 1 1 1 1 Cycles 5 6 7 6 Z S C -
Notes: I affected - not affected Figure 2.5 Multiplication
RAM
0 1 2
0 1 2
Figure 2.6 Division
RAM
i-1 i i+1
i
j-1
j-1 j j+1
j j+1
253 254 255
253 254 255
REG. j
REG. j+1
:
REG. i
REG. j
X
16 Bit
REG. i
REMAINDER
QUOTIENT
LSB
MSB
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3 EPROM EPROM memory provides an on-chip userprogrammable non-volatile memory, which allows fast and reliable storage of user data. EPROM memory can be locked by the user. In fact, a memory location called Lock Cell is devoted to lock EPROM and avoid external operations. A software identification code, called ID CODE, distinguishes which software version is stored in the memory. 64 kbits of memory space with an 8-bit internal parallelism (up to 8 kbytes) addressed by an 13-bit bus are available. The data bus is 8 bits. Memory has a double supply: VPP is equal to 12V5% in Programming Phase or to VSS during Working Phase. VDD is equal to 5V10%. ST52X430 EPROM memory is divided into three main blocks (see Figure ): s Interrupt Vectors memory block (3 through 20) contains the addresses for the interrupt routines. Each address is composed of three bytes.
s s
The maximum value of MemAdd is 1023. This area is dynamically assigned according to the size of the fuzzy routines. The unused memory area, if any, is assigned to the Program Instruction Set memory block. The Program Instructions Set memory block (MemAdd through MemAddx) contains the instruction set of the user program. The following table summarizes the values of Mem Addx for the different devices
s
Table 3.1 Mem Addx
ST52T430K1 Me m 2047 ST52T430 4095 ST52T430 8191
Mbfs Setting memory block (21 through MemAdd) contains the coordinates of the vertexes of every Mbf defined in the program.
Locations 0, 1 and 2 contain the address of the first microcode instruction.The operations that can be performed on EPROM during the Programming Phase are: Stand By, Memory Writing, Reading and Verify/Margin Mode, Memory Lock, IDCode Writing and Verify.
Figure 3.1 Program Memory Organization
ST52430K3
8191
ST52430K2
4095 2047 Fuzzy and Boolean Algorithms
ST52430K1
Program Instruction Set
MemAdd+1 MemAdd Mbfs Parameters 21 20 INT_EXT INT_SCI INT_TIMER/PWM2 INT_TIMER/PWM1 INT_TIMER/PWM0 INT_ADC Program Instruction First Address
Mbfs Setting and Program Instruction Set
Interrupt Vectors
3 2 0
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Table 3.2 EPROM Control Register
OPERATION Stand By Memory Reading/Verify Memory Unlock and Lock Status Reading Memory Writing Memory Lock ID CODE Writing Memory Lock Status Reading/Verify ID CODE Reading/ Verify REGISTER VALUE 0 1 2 3 4 5 9
The operations above are managed by using the internal 4-bit EPROM Control Register. The reading phase is executed with VPP= 5V5%, while the verify/Margin Mode phase needs VPP= 12V5%. The Blank Check must be a reading operation with VPP= 5V5%. Table 3.2 illustrates EPROM Control Register codes used to identify the operation running. 3.1 EPROM Programming Phase Procedure The Programming mode is selected by applying 12V5% voltage or 5V5% voltage to the VPP pin and setting the control signal as following: RESET =Vss TEST =Vss If the VPP voltage is 5V5% only reading may be performed. RST_ADD, INC_ADD, RST_CONF, INC_CONF and PHASE are the control signals used during the Programming Mode. PHASE, RST_CONF and RST_ADD signals are active on level, the others are active on rising edge.
10
Figure 3.2 Eprom Programming Timing
VALID DATA
VALID DATA
VALID DATA
PA(0:7)
DATA OUT
DATA IN
DATA OUT
DATA OUT
RST_ADD
RST_CONF
INC_ADD
INC_CONF
PHASE
100nS
10S
MEMORY UNLOCK
MEMORY WRITING LOCATION ADDRESS =1
MEMORY VERIFY MARGIN MODE
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PHASE and RST_ADD signals are active low, RST_CONF signal is active high. Port A is used for the memory data I/O. (See Table 3.2 for pin reference on the different packages). Memory may be locked by means of the Memory Lock Status, which is a flag used to enable EPROM operations. If Memory Lock Status is 1 all EPROM operations are enabled, otherwise the user may only read (and verify) the OTP code and the Memory Lock Status. Only if EPROM is not locked by means of Lock Cell (see EPROM Locking may EPROM operations be enabled by changing the Memory Lock Status from 0 to 1. RST_ADD signal resets the memory address register and the Memory Lock Status. When the RST_ADD becomes high, the memory must be unlocked in order to read or write. INC_ADD signal increments the memory address. RST_CONF signal resets the EPROM Control Register. When RST_CONF is high, the DATA I/ O Port A is in output, otherwise it is always in input. INC_CONF signal increments the EPROM Control Register value. PHASE signal validates the operation selected by means of the EPROM Control Register value. 3.1.1 EPROM Operation. In order to execute an EPROM operation (See Table 3.2), the corresponding identification value must be loaded in the EPROM Control Register. The signal timing is the following: RST_ADD= high and PHASE= high, RST_CONF changes from low to high level, to reset the EPROM Control Register, and INC_CONF signal generates a number of positive pulses equal to the value to be loaded. After this sequence, a negative pulse of the PHASE signal will validate the operation selected. The minimum PHASE signal pulse width must be 10 s for EPROM Writing Operation and 100 ns for the others. When RST_CONF is high, DATA I/O Port A is enabled in output and the reading/verifying operation results are available. After a writing operation, when RST_CONF is high, Port A is in output without valid data. 3.1.2 EPROM Locking. The Memory Lock operation, which is identified with the number 4 in the EPROM Control Register, writes "0" in the Memory Lock Cell. At the beginning of an External Operation, when the RST_ADD signal changes from low level to high level, the Memory Lock Status is "0", therefore it must be unlocked before proceeding. In order to unlock the Memory Lock Status the operation, which is identified by the number 2 in the EPROM Control Register must be executed (see Figure 3.2). Memory Lock Status can be changed only if Memory Lock Cell is "1". After a Memory Lock operation external operations cannot be executed except to read (or verify) the OTP Code and the Memory Lock Status. 3.1.3 EPROM Writing. When the memory is blank, all bits are at logic level "1". Data is introduced by programming only the zeros in the desired memory location. However, all input data must contain both "1" and "0". The only way to change "0" into "1" is to erase the entire memory (by exposure to Ultra Violet light) and reprogram it. The memory is in Writing mode when the EPROM Control Register value is 3. The VPP voltage must be 12V5%, with stable data on the data bus PA(0:7). The timing signals are the following (see Figure ): 1) RST_ADD and RST_CONF change from low to high level, 2) two pulses on INC_CONF signal load the Memory Unlock operation code, 3) a negative pulse (100 ns) on the PHASE signal validates the Memory Unlock operation, 4) a negative pulse on RST_CONF signal resets the EPROM Control Register, 5) three positive pulses on INC_CONF load the Memory Writing operation code, 6) a train of positive pulses on INC_ADD signal increments the memory location address up to the requested value (generally this is a sequential operation and only one pulse is used), 7) a negative pulse (10 s) on the PHASE signal validates the Memory Writing operation.
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3.1.4 EPROM Read/Verify Margin Mode. The read phase is executed with VPP= 5V5%, instead of the verify phase that needs VPP= 12V5%. The Memory Verify operation is available in order to verify the accuracy of the data written. A Memory Verify Margin Mode operation can be executed immediately after writing each byte, in this case (see Figure ): 1) a positive pulse on RST_CONF signal resets the EPROM Control Register, if it wasn't already reset; 2) one positive pulse on INC_CONF loads the Memory Read/Verify operation code; 3) a negative pulse (100 ns) on the PHASE signal validates the Memory Reading / Verify operation; 4) a negative pulse on RST_CONF signal puts in the PA(0:7) port the value stored in the actual memory address and resets the EPROM Control Register; If an error occurred writing, the user has to repeat EPROM writing. 3.1.5 Stand by Mode. EPROM has a standby mode, which reduces the active current from 10mA (Programming mode) to less than 100 A. Memory is placed in standby mode by setting the PHASE signal at a high level or when the EPROM Control Register value is 0 and the PHASE signal is low. 3.1.6 ID code. A software identification code, called ID code may be written in order to distinguish which software version is stored in the memory. 64 Bytes are dedicated to store this code by using the address values from 0 to 63. The ID Code may be read or verified even if the Memory Lock Status is "0". The timing signals are the same as that of a normal operation. 3.2 Eprom Erasure The transparent window available in the CSDIP32W package, allows the memory contents to be erased by exposure to UV light. Erasure begins when the device is exposed to light with a wavelength shorter than 4000A. Sunlight, as well as some types of artificial light, includes wavelengths in the 3000-4000A range which, on prolonged exposure can cause erasure of memory contents. Therefore, it is recommended that EPROM devices be fitted with an opaque label over the window area in order to prevent unintentional erasure. The erasure procedure recommended for EPROM devices consists of exposure to short wave UV light having a wavelength of 2537A. The minimum integrated dose recommended (intensity x exposure time) for complete erasure is 15Wsec/cm 2. This is equivalent to an erasure time of 15-20 minutes using a UV source having an intensity of 12mW/cm 2 at a distance of 25mm (1 inch) from the device window.
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4 INTERRUPTS The Control Unit (CU) responds to peripheral events and external events via its interrupt channels. When such an events occur, if the related interrupt is not masked and according to a priority order, the current program execution can be suspended to allow the CU to execute a specific response routine. Each interrupt is associated with an interrupt vector that contains the memory address of the related interrupt service routine. Each vector is located in the Program Space (EPROM Memory) at a fixed address (see Interrupt Vectors Table 4.2). 4.1 Interrupt Operation If there are pending interrupts at the end of an arithmetic or logic instruction, the one with the highest priority is passed. Passing an interrupt means storing the arithmetic flags and the current PC in the stack and executing the associated Interrupt routine, whose address is located in three bytes of the EPROM memory location between address 3 and 20. The Interrupt routine is performed as a normal code, checking if a higher priority interrupt has to be passed at the end of each instruction. An Interrupt request with the higher priority stops the lower priority Interrupt. The Program Counter and the arithmetic flags are stored in the stack. With the RETI (Return from Interrupt) instruction the arithmetic flags and Program Counter (PC) are restored from the top of the stack. This stack was already described in section RAM and STACK. An Interrupt request cannot stop processing of the fuzzy rule, but this is passed only after the end of a fuzzy rule or at the end of a logic, or arithmetic instruction. NOTE: A fuzzy routine can only be interrupted in the Main program. An interrupt request cannot stop a Fuzzy function that is running inside another interrupt routine. In order to use a Fuzzy function inside an interrupt routine, the user MUST include the Fuzzy function between an UDGI (MDGI) instruction and an UEGI (MEGI) instruction (see the following paragraphs), so that the interrupt request may be disabled during the execution of the fuzzy function. 4.2 Global Interrupt Request Enabling When an Interrupt occurs, it generates a Global Interrupt Pending (GIP), that can be masked by software. After a GIP a Global Interrupt Request (GIR) will be generated and Interrupt service Figure 4.1 Interrupt Flow
NM OR AL PRO AM GR FLOW IN TERRU PT SER E VIC R TIN OU E
IN TERR UPT
R ETI IN STRU CTIO N
Figure 4.2 Interrupt Vectors mapping
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
INT_ADC
INT_TIMER/PWM0
INT_TIMER/PWM1 INTERRUPT VECTORS
INT_TIMER/PWM2
INT_SCI
INT_EXT
Figure 4.3 Global Interrupt Request generation
Global Interrupt Pending User Global Interrupt Mask Macro Global
Global Interrupt Request
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Routine associated to the interrupt with higher priority will start. In order to avoid possible conflicts between interrupt masking set in the main program, or inside high level language compiler macros, the GIP is hung up through the User Global Interrupt Mask or the Macro Global Interrupt Mask (see Figure 4.2). UEGI/UDGI instruction switches on/off the User Global Interrupt Mask, enabling/disabling the GIR for the main program. MEGI/MDGI instructions switch the Macro Global Interrupt Mask on/off, in order to ensure that the macro will not be broken. 4.3 Interrupt Sources ST52X430 manages interrupt signals generated by the internal peripherals (PWM/Timers, UART and Analog to Digital Converter) or coming from the INT/PC0 pin. The External Interrupt can be programmed to be active on the rising or falling edge of INT/PC0 signal by setting the PEXTINT bit of the Configuration Register to 0. WARNING: Changing the interrupt priority an interrupt request is generated. Each peripheral can be programmed in order to generate the associated interrupt; further details are described in the related chapter. 4.4 Interrupt Maskability The interrupts can be masked by configuring the REG_CONF 0 by means of LDCR, or LDCE, instruction. The interrupt is enabled when the bit associated to the mask interrupt is "1". Viceversa, when the bit is "0", the interrupt is masked and is kept pendent. For example: LDRC 10,6 //load the constant 6 in the RAM Register 10 LDCR 0, 10 // set the CONF_REG 0 with the value stored in the RAM Register 10 the result is CONF_REG0 =00000110 enabling the interrupts deriving from the ADC (INT_ADC) and from the PWM/TIMER 0 (INT_PWM/TIMER0). Table 4.1 Configuration Register 0 Description
Bit Name Value 0 0 MSKE 1 External Interrupt Not Masked A/D Converter Interrupt Masked A/D Converter Interrupt Not Masked PWM/TIMER 0Interrupt Masked PWM/TIMER 0 Interrupt Not Masked PWM/TIMER 1 Interrupt Masked PWM/TIMER 1 Interrupt Not Masked PWM/TIMER 2 Interrupt Masked PWM/TIMER 2 Interrupt Not Masked SCI Interrupt Masked SCI Interrupt Not Masked External Interrupt Polarity Active on Rising External Interrupt Polarity Active on Falling Description External Interrupt Masked
0 1 MSKAD 1
0 2 MSKTM0 1
0 3 MSKTM1 1
0 4 MSKTM2 1
0 5 MSCI 1
0 6 PEXTINT 1
7
Not used
Reset Configuration `000000'
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Table 4.2
Interrupts Description
Description ADC PWM/TIMER 0 Int Int Priority Programmable Programmable Peripheral Code 000 001 Maskable yes yes EPROM Locations 3-5 6-8
Name INT_ADC INT_PWM/ TIMER0 INT_PWM/ TIMER1 INT_PWM/ TIMER2 INT_SCI INT_EXT
PWM/TIMER 1
Int
Programmable
010
yes
9-11
PWM/TIMER 2 SCI External Interrupt (INT)
Int Int Ext
Programmable Programmable Highest
011 100 -
yes yes yes
12-14 15-17 18-20
Figure 4.4 Interrupt Configuration Register 0
REG_CONF0 Interrupts Mask D7 D6 D5 D4 D3 D2 D1 D0 MSKE: Ext. Int. MSKAD: A/D Int. MSKTM0: Timer0 Int. MSKTM1: Timer1 Int. MSKTM2: Timer2 Int. MSCI: SCI Int. PEXTINT: Ext. Int. Polariry Not Used
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Figure 4.5 Interrupt Configuration Register 17 & 18
Interrupts Priority REG_CONF18 D15 D14 D13 D12 D11 D10 D9 D8 REG_CONF17 D7 D6 D5 D4 D3 D2 D1 D0 INT 1 INT 2 INT 3 INT 4 INT 5 Not Used
4.5 Interrupt Priority Seven priority levels are available: level 6 has the lowest priority, level 0 has the highest priority. Level 6 is associated to the Main Program, levels 5 to 1 are programmable by means of the priority registers called REG_CONF17 and REG_CONF18 (see Figure 4.5 and Table 4.3); whereas the higher level is related to the external interrupt (INT_EXT). PWM/Timers, UART and ADC are identified by a three-bit Peripheral Codes (see Table 4.2); in order to set the i-th priority level the user must write the peripheral label i in the related INTi priority level. i.e. LDRC 10, 193 //(load the value 193='11000001' in the RAM Register 10) LDRC 11, 168 //(load the value 168='10101000' in the RAM Register 11) LDCR 17, 10 // set the REG_CONF17= `11000001' LDCR 18, 11 // set the REG_CONF18= `10101000' The following priority levels are defined: s Level 1: INT_PWM/TIMER0 (PWM/TIMER 0 Code: 001)
s
Table 4.3 Conf. Register 17 & 18 Description
Bit Name Value Periphera l Code Periphera l Code Periphera l Code Periphera l Code Periphera l Code Level
0, 1,2
INT1
High
3, 4,5
INT2
Medium-High
6,7,8
INT3
Medium-Low
9,10,11
INT4
Low
12,13,1 4
s
INT5
Very Low
Level 3: Int_PWM/Timer2 (PWM/TIMER 2 Code: 011) Level 4: INT_UART (UART Code: 100) Level 5: INT_PWM/TIMER1 (PWM/TIMER 1 Code: 010)
s s
Level 2: INT_ADC (ADC Code: 000)
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Figure 4.6 Example of a sequence of Interrupt requests
INT2 PRIORITY LEVEL INT0 INT4
Table 4.4 RINT Instruction code INT1 INT3
Peripheral Name Value 2 3 4 5
0
INT0
PWM/TIMER 1
1 INT1
PWM/TIMER 2 SCI
2
INT2
INT2
INT2
External Interrupt
3 INT3
4
INT4
5
6
MAIN PROGRAM
MAIN PROGRAM
REMARK: The Interrupt priority must be set at the beginning of the main program, because at the RESET REG_CONF1='00000000', this condition could generate wrong operations. Further, changing the priority levels must be avoided in interrupt service routines. When a source provides an Interrupt request and the request processing is also enabled, the CU changes the normal sequential flow of a program by transferring program control to a selected service routine. When an interrupt occurs the CU executes a JUMP instruction to the address loaded in the related location of the Interrupt Vector. When the execution returns to the original program it immediately begins following the instruction that was interrupted.
4.6 Interrupts and Low power mode All interrupts allow the processor to leave the WAIT low power mode. Only the external Interrupt allows the processor to leave the HALT low power mode. 4.7 Interrupt RESET An eventually pending interrupt can be reset with the instruction RINT j, which resets the interrupt j-th where j identifies the peripherals as described in the following table (see Table 4.4). The assembler instruction: RINT 2 Resets the PWM/Timer 1 interrupt. Note: The RINT command must be preceded from a UDGI (or MDGI) command and followed by a UEGI (or MEGI) command. WARNING: If an interrupt is reset, with the RINT instruction within its own interrupt routine, the priority level of the interrupt becomes the lowest and the routine can be immediately interrupted by a lower priority interrupt request.
Table 4.4 RINT Instruction code
Peripheral Name A/D Converter PWM/TIMER 0 Value 0 1
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5 CLOCK, RESET & POWER SAVING MODE 5.1 System Clock The ST52X430 Clock Generator module generates the internal clock for the internal Control Unit, ALU and on-chip peripherals and it is designed to require a minimum number of external components. The ST52X430 oscillator circuit generates an internal clock signal with the same period and phase as that of the OSCin input pin. The maximum frequency allowed is 20 Mhz. Note: When the SCI peripheral is used only a 5, 10, or 20 MHz system clock must be used. The system clock may be generated by using either a quartz crystal, ceramic resonator or an external clock. The different methods of the clock generator are illustrated in Figure 5.1. When an external clock is used, it must be connected on the OSCin pin, while OSCout can be floating. The crystal oscillator start-up time is a function of many variables: crystal parameters (especially Rs), oscillator load capacitance (CL), IC parameters, environment temperature, supply voltage. Figure 5.1 Oscillator Connections Note: The crystal or ceramic leads and circuit connections must be as short as possible. Typical values for CL1, CL2 are 10pF for a 20 MHz crystal. 5.2 RESET There are two Reset sources: - RESET pin (external source.) - WATCHDOG (internal source) When a Reset event happens, the user program restarts from the beginning. The Reset pin is an input. An internal reset does not affect this pin. A Reset signal originated by external sources is recognized instantaneously. The RESET pin may be used to ensure VDD has risen to a point where the MCU can operate correctly before the user program runs. In working mode Reset must be set to `1' (see Table 2.1). 5.3 Power Saving Mode There are two Power Saving modes: WAIT and HALT mode. These conditions may be entered using the WAIT or HALT instructions. 5.3.1 Wait Mode Wait mode places the MCU in low power consumption by stopping the CPU. All peripherals
CRYSTAL CLOCK
EXTERNAL CLOCK
ST52X430
OSCin OSCout OSCin
ST52X430
OSCout
Cl1 10pF
Cl2 10pF
CLOCK INPUT
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and the watchdog remain active. During WAIT mode, Interrupts are enabled. The MCU will remain in Wait mode until an Interrupt or a RESET occurs, whereupon the Program Counter jumps to the interrupt service routine or, if a RESET occurs, at the beginning of the user program. REMARK: In Wait mode the CPU clock does not stop. 5.3.2 Halt Mode Halt mode is MCU's lowest power consumption mode, which is entered by executing the HALT instruction. The internal oscillator is turned off, causing all internal processing to stop, including the operations of the on-chip peripherals. Figure 5.2 Reset Block Diagram Halt mode cannot be used when the watchdog is enabled. If the HALT instruction is executed while the watchdog system is enabled, it will be skipped without modifying the normal CPU operations. The ICU can exit Halt mode after an external interrupt or reset. The oscillator is then turned on and stabilization time is provided before restarting CPU operations. Stabilization time is 4096 CPU clock cycles after the interrupt and 1.000.000 after the Reset. After the start up delay, the CPU restarts operations by serving the external interrupt routine. Reset makes the ICU exit from HALT mode and restart, after the delay, from the beginning of the user program after the delay. Warning: if the External Interrupt is disabled, the ICU exits from the Halt mode and jumps to the lower priority interrupt routine. Figure 5.4 WAIT Flow Chart
RESET INTERNAL RESET
WATCHDOG RESET
Figure 5.3 Simple Reset Circuit
Vcc 100 F 10k
RESET 2.2k 2.2k 1F
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Figure 5.5 HALT Flow Chart
HALT INSTRUCTION
YES WATCHDOG ENABLED
NO HALT INSTRUCTION SKIPPED
OSCILLATOR PERIPHERALS CLOCK CPU CLOCK
OFF OFF OFF
NO NO RESET EXTERNAL INTERRUPT YES
YES
OSCILLATOR PERIPHERALS CLOCK CPU CLOCK
ON ON ON
OSCILLATOR PERIPHERALS CLOCK CPU CLOCK
ON ON ON
1000000 CPU CLOCK CYCLES DELAY
4096 CPU CLOCK CYCLES DELAY
RESET CPU AND RESTART USER PROGRAM
NO
EXTERNAL INTERRUPT ENABLED
YES
RESTART PROGRAM SERVICING THE LOWER PRIORITY INTERRUPT ROUTINE
RESTART PROGRAM SERVICING THE EXTERNAL INTERRUPT ROUTINE
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6 I/O PORTS 6.1 Introduction ST52X430 devices feature flexible individually programmable multi-functional input/output lines. Refer to the following figure for specific pin allocations. 23 I/O lines, grouped in 3 different ports are available on the ST52X430: PORT A = 7 or 8-bit ports (PA0 - PA7 pins) PORT B = 7 or 8-bit ports (PB0 - PB7 pins) PORT C = 8-bit port (PC0 - PC7 pins) PIN 24 in the SO34 or PIN 22 in the PDIP32 can be configured to belong to port A or to port B. These I/O lines can be programmed to provide digital input/output and analog input, or to connect input/output signals to the on-chip peripherals as alternate pin functions. Input buffers are TTL compatible with Schmitt trigger in port A and C while port B is CMOS compatible without Schmitt trigger. The output buffer can supply up to 8 mA. The port cannot be configured to be used contemporaneously as input and output. Figure 6.1 Ports A & C Functional Blocks Each port is configured by using two configuration registers. The first is used to determine if a pin is an input or output, while the second defines the Alternate functions. 6.2 Input Mode The input configuration is selected by setting the corresponding configuration register bit to "1" (REG_CONF 4, 13 and 15) (see paragraph I/O Port Configuration Registers). The ports are configured by using the configuration registers illustrated in the following table. . Table 6.1 I/O Port Configuration Registers.
PORT A Reg_Conf 4 PORT B Reg_Conf 13 PORT C Reg_Conf 15
Digital input data is automatically stored in the Input Registers, but it cannot be read directly. In order to read a single bit of the IR its value must be copied in a RAM location. Digital data is stored in a RAM location by using the assembler instruction: LDRI RAM_Reg Input_i
TO INPUT REGISTER and PERIPHERALS
TTL
PORT A PIN or PORT C PIN
FROM PERIPHERAL FROM OUTPUT REGISTER
FROM CONFIGURATION REGISTER
FROM CONFIGURATION REGISTER
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Figure 6.2 Port B Functional Blocks
FROM CONFIGURATION REGISTER CMOS TO INPUT REGISTER
PORT B PIN
TO A/D CONVERTER
FROM OUTPUT REGISTERS
FROM CONFIGURATION REGISTER
Table 6.2
PORT A IR 9
Input Register and I/O Ports
PORT B IR 10 PORT C IR 11
6.3 Output Mode The output configuration is selected by setting the corresponding configuration register bit to "0" (REG_CONF 4, 13 and 15) (see paragraph I/O Port Configuration Registers). Digital data is transferred to the related I/O Port by means of the Output register via the assembler instructions LDPE or LDPR.
Table 6.3 Output Register and I/O Ports
PORT A OR 0 PORT B OR 1 PORT C OR 2
6.4 Alternate Functions Several ST52X430 pins are configurable to be used with different functions (see Table 1.1). When an on-chip peripheral is configured to use a pin, the correct I/O mode of the related pin must be selected. For example: if pin 26 (PA5/T0CLK in the SO34) has to be used as an external PWM/Timer0 clock, the Reg_Conf 4(5) bit must be set to `1'. When the signal is an on-chip peripheral input the related I/O pin has to be configured in Input Mode. When a pin is used as an A/D Converter input the related I/O pin is automatically set in tristate. The analog multiplexer (controlled by the A/D configuration Register) switches the analog voltage present on the selected pin to the common analog rail, which is connected to the ADC input. It is recommended that the voltage level not be changed or that any port pins not be loaded while conversion is running. Furthermore, it is recommended that clocking pins not be located close to a selected analog pin. 6.5 I/O Port Configuration Registers The I/O mode for each bit of the three ports is selected by using the Configuration Registers 4,
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13 and 15 (See Table 6.1) The structure of these registers is illustrated in the following tables. Each bit of the configuration registers determines the I/O mode of the related port pin. Table 6.4 Ports A REG_CONF 4
Bit Name Value 0 0 D0 1 0 1 D1 1 0 2 D2 1 0 3 D3 1 0 4 D4 1 0 5 D5 1 0 6 D6 1 0 7 D7 1 Description Set the pin PA0/T0RES in Output Mode Set the pin PA0/T0RES in Input Mode Set the pin PA1/T0OUT in Output Mode Set the pin PA1/T0OUT in Input Mode Set the pin PA2/T1OUT in Output Mode Set the pin PA2/T1OUT in Input Mode Set the pin PA3/T2OUT in Output Mode Set the pin PA3/T2OUT in Input Mode Set the pin PA4/T0STRT in Output Mode Set the pin PA4/T0STRT in Input Mode Set the pin PA5/T0CLK in Output Mode Set the pin PA5/T0CLK in Input Mode Set the pin PA6 in Output Mode Set the pin PA6 in Input Mode Set the pin PB7/PA7/ Ain7 in Output Mode Set the pin PB7/PA7/ Ain7 in Input Mode 7 D7 1 6 D6 1 0 5 D5 1 0 4 D4 1 0 3 D3 1 0 2 D2 1 0 1 D1 1 0 0 D0 1 0
Table 6.5 Ports B REG_CONF 13
Bit Name Value 0 Description Set the pin PB0/Ain0 in Output Mode Set the pin PB0/Ain0 in Input Mode Set the pin PB1/Ain1 in Output Mode Set the pin PB1/Ain1 in Input Mode Set the pin PB2/Ain2 in Output Mode Set the pin PB2/Ain2 in Input Mode Set the pin PB3/Ain3 in Output Mode Set the pin PB3/Ain3 in Input Mode Set the pin PB4/Ain4 in Output Mode Set the pin PB4/Ain4 in Input Mode Set the pin PB5/Ain5 in Output Mode Set the pin PB5/Ain5 in Input Mode Set the pin PB6/Ain6 in Output Mode Set the pin PB6/Ain6 in Input Mode Set the pin PB7/PA7/ Ain7 in Output Mode Set the pin PB7/PA7/ Ain7 in Input Mode
Reset Configuration `11111111'
Reset Configuration `11111111'
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Table 6.6 Port C REG_CONF 15
Bit Name Value Description Set the pin INT/PC0 in Output Mode
Analog Input Option. The PB0-PB7 pins can be configured to be analog inputs according to the codes programmed in the configuration register REG_CONF 14 (See Table 6.7). These analog inputs are connected to the on-chip 8-bit Analog to Digital Converter. Table 6.7 Analog Inputs (REG_CONF 14)
0 0 D0 1
Set the pin INT/PC0 in Input Mode Set the pin T0OUT/ PC1 in Output Mode Set the pin T0OUT/ PC1 in Input Mode Set the pin T1OUT/ PC2 in Output Mode
Bit 0 1 2
Name D0 D1 D2 D3 D4 D5 D6 D7
Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Description pin PB0/Ain0 Digital I/O pin PB0/Ain0 Analog pin PB1/Ain1 Digital I/O pin PB1/Ain1 Analog pin PB2/Ain2 Digital I/O pin PB2/Ain2 Analog pin PB3/Ain3 Digital I/O pin PB3/Ain3 Analog pin PB4/Ain4 Digital I/O pin PB4/Ain4 Analog pin PB5/Ain5 Digital I/O pin PB5/Ain5 Analog pin PB6/Ain6 Digital I/O pin PB6/Ain6 Analog pin PB7/Ain7 Digital I/O pin PB7/Ain7 Analog
0 1 D1 1
0 2 D2 1
3 Set the pin T1OUT/ PC2 in Input Mode Set the pin T2OUT/ PC3 in Output Mode Set the pin T2OUT/ PC3 in Input Mode Set the pin Tx/PC4 in Output Mode Set the pin Tx/PC4 in Input Mode Set the pin Rx/PC5 in Output Mode Set the pin Rx/PC5 in Input Mode Set the pin PC6 in Output Mode Set the pin PC6 in Input Mode Set the pin PC7 in Output Mode Set the pin PC7 in Input Mode 4 5 6 7
0 3 D3 1
0 4 D4 1
Reset Configuration `11111111'
0 5 D5 1
0 6 D6 1
0 7 D7 1
Reset Configuration `11111111'
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PWM/Timers Alternate Functions The pins of Port A and C can be configured to be I/ O of the three PWM/Timers available on the ST52X430. The configuration of these pins is performed by using the Configuration Registers REG_CONF 12 and REG_CONF 16 if the related pin has to be output. When the related pin has to be used as an input peripheral the configuration is performed by the relative peripheral configuration registers (See PWM/Timer Session). Table 6.8 PWM/Timers REG_CONF 16 Bit Name Value
1 0 PC1 0
Table 6.9 PWM/Timers REG_CONF 12
Bit Name Value Description Pin PA1/T0OUT is configured as PWM/Timer 0 complementary output Pin PA1/T0OUT is configured as Port A Digital I/O Pin PA2/T1OUT is configured as PWM/Timer 1 complementary output Pin PA2/T1OUT is configured as Port A Digital I/O Pin PA3/T2OUT is configured as PWM/Timer 2 complementary output Pin PA3/T2OUT is configured as Port A Digital I/O
1 0 PA1 0
Description
Pin T0OUT/PC1 is configured as Port C Digital I/O 1 Pin T0OUT/PC1 is configured as PWM/ Timer 0 output T0OUT PinT1OUT/PC2 is configured as Port C Digital I/O Pin T1OUT/PC2 is configured as PWM/ Timer 1 output T1OUT Pin T2OUT/PC3 is configured as Port C Digital I/O Pin T2OUT/PC3 is configured as PWM/ Timer 2 output T2OUT Pin Tx/PC4 is configured as Port C Digital I/O Pin Tx/PC4 is configured as SCI output Tx Not Used 4-7 NC 1 3 PASZ 0 2 PA3 0 PA2 0 1
1 1 PC2 0
1
1 2 PC3 0
PORT A bits = 8
PORT A bits = 7
1 3 PC4 0
x
Not Used
Reset Configuration `0000'
4-7
NC
X
Reset Configuration `1111'
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Figure 6.3 Configuration Register 12
REG_CONF 12 DIGITAL PORT D7 D6 D5 D4 D3 D2 D1 D0
PA1T: Pin PA1/T0OUT setting PA2T: Pin PA2/T1OUT setting PA3T: Pin PA3/T2OUT setting PA78: PORT A size not used
Figure 6.4 Configuration Register 16
REG_CONF 16 DIGITAL PORT D7 D6 D5 D4 D3 D2 D1 D0
P6SL: Pin T0OUT/PC1setting P7SL: Pin T1OUT/PC2 setting P8SL: Pin T2OUT/PC3 setting P9SL: Pin Tx/PC4 setting not used
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7 FUZZY COMPUTATION (DP) The ST52T430/E430 Decision Processor (DP) main features are: s Up to 8 Inputs with 8-bit resolution;
s
Figure 7.2 Alpha Weight Calculation
1
j-th Mbf
1 Kbyte of Program/Data Memory available to store more than 300 to Membership Functions (Mbfs) for each Input; Up to 128 Outputs with 8-bit resolution; Possibility of processing fuzzy rules with an UNLIMITED number of antecedents; UNLIMITED number of Rules and Fuzzy Blocks.
ij
i-th INPUT VARIABLE
s s
s
The limits on the number of Fuzzy Rules and Fuzzy program blocks are only related to the Program/Data Memory size. 7.1 Fuzzy Inference The block diagram shown in Figure 7.1 describes the different steps performed during a Fuzzy algorithm. The ST52T430/E430 Core allows for the implementation of a Mamdani type fuzzy inference with crisp consequents. Inputs for fuzzy inference are stored in 8 dedicated Fuzzy input registers. The LDFR instruction is used to set the Input Fuzzy registers with values stored in the Register File. The result of a Fuzzy inference is stored directly in a location of the Register File. 7.2 Fuzzyfication Phase In this phase the intersection (alpha weight) between the input values and the related Mbfs (Figure 7.2) is performed. Eight Fuzzy Input registers are available for Fuzzy inferences. Figure 7.1 Fuzzy Inference
After loading the input values by using the LDFR assembler instruction, the user can start the fuzzy inference by using the FUZZY assembler instruction. During fuzzyfication: input data is transformed in the activation level (alpha weight) of the Mbf's. 7.3 Inference Phase The Inference Phase manages the alpha weights obtained during the fuzzyfication phase to compute the truth value () for each rule. This is a calculation of the maximum (for the OR operator) and/or minimum (for the AND operator) performed on alpha values according to the logical connectives of Fuzzy Rules. Several conditions may be linked together by linguistic connectives AND/OR, NOT operators and brackets. The truth value and the related output singleton are used by the Defuzzyfication phase, in order to complete the inference calculation.
11
1
1m
2
FUZZYFICATION
n1 nm
INFERENCE PHASE
N rules -1 N rules
DEFUZZYFICATION
Input Values
Output Values
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Figure 7.3 Fuzzyfication 7.5 Input Membership Function The Decision Processor allows the management of triangular Mbfs. In order to define an Mbf, three different parameters must be stored on the Program/Data Memory (see Figure 7.4): s the vertex of the Mbf: V;
s
IF INPUT 1 IS X1 OR INPUT 2 IS X2 THEN .......
1 2 X1
Input 1
the length of the left semi-base: LVD; the length of the right semi-base: RVD;
X2
Input 2
s
OR = Max
IF INPUT 1 IS X1 AND INPUT 2 IS X2 THEN .......
1 2 X1
Input 1
In order to reduce the size of the memory area and the computational effort the vertical range of the vertex is fixed between 0 and 15 (4 bits) By using the previous memorization method different kinds of triangular Membership Functions may be stored. Figure 7.5 shows some examples of valid Mbfs that can be defined in ST52T430/ E430. Each Mbf is then defined storing 3 bytes in the first Kbyte of the Program/Data Memory. The Mbf is stored by using the following instruction: MBF n_mbf lvd v rvd
X2
Input 2
7.4 Defuzzyfication In this phase the output crisp values are determined by implementing the consequent part of the rules. Each consequent Singleton Xi is multiplied by its weight values i, calculated by the Decision processor, in order to compute the upper part of the Defuzzyfication formula. Each output value is obtained from the consequent crisp values (Xi) by carrying out the following Defuzzyfication formula:
N
where: n_mbf is a tag number that identifies the Mbf lvd, v, and rvd are the parameters that describe the Mbf's shape as described above. Figure 7.4 Mbfs Parameters
15
Input Mbf
X ij ij
j Y i = -------------------N
0
V LVD
Input Variable RVD
ij
j
where: i = identifies the current output variable N = number of the active rules on the current output ij = weight of the j-th singleton Xij = abscissa of the j-th singleton The Decision Processor outputs are stored in the RAM location i-th specified in the assembler instruction OUT i.
15 w
Output Singleton
0
X
Output Variable
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Figure 7.5 Example of valid Mbfs Figure 7.6 Output Membership Functions
j-th Singleton
1 ij i0 in
0
X
i0
X
ij
X
i-th OUTPUT
in
7.6 Output Singleton The Decision Processor uses a particular kind of membership function called Singleton for its output variables. A Singleton doesn't have a shape, like a traditional Mbf, and is characterized by a single point identified by the couple (X, w), where w is calculated by the Inference Unit as described earlier. Often, a Singleton is simply identified with its Crisp Value X. Table 7.1 Fuzzy Instructions Set
Instruction MBF n_mbf Ivd v rvd LDP n m LDN n m FZAND FZOR LDK SKM LDM CON crisp OUT n_out FUZZY
7.7 Fuzzy Rules Rules can have the following structures: if A op B op C...........then Z if (A op B) op (C op D op E...) ...........then Z where op is one of the possible linguistic operators (AND/OR) In the first case the rule operators are managed sequentially; in the second one, the priority of the operator is fixed by the brackets. Each rule is codified by using an instruction set, the inference time for a rule with 4 antecedents and 1 consequent is about 3 microseconds at 20 MHz. The Assembler Instruction Set used to manage the Fuzzy operations is reported in the table below.
Description Stores the Mbf n_mbf with the shape identified by the parameters Ivd, v and rvd Fixes the alpha value of the input n with the Mbf m and stores it in internal registers Calculates the complementary alpha value of the input n with the Mbf m. and stores the result in internal registers Implements the Fuzzy operation AND between the last two values stored in internal registers Implements the Fuzzy operation OR between the last two values stored in internal registers Stores the result of the last Fuzzy operation executed in internal registers Loads the result of the last performed Fuzzy operation (stored in the temporary register K) in the temporary buffer M. Copies the value of register M in the data stack Multiplies the crisp value with the last weight Performs Defuzzyfication and stores the currently Fuzzy output in the RAM n_out location Starts the Fuzzy algorithm
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Example 1:
IF Input 1 IS NOT Mbf1 AND Input4 is Mbf12 OR Input3 IS Mbf8 THEN Crisp1
is codified by the following instructions: LDN 1 1 LDP 4 12 FZAND LDK LDP 3 8 FZOR calculates the NOT value of Input1 with Mbf1 and stores the result in internal registers fixes the value of Input4 with Mbf12 and stores the result in internal registers implements the operation AND between the results obtained with the previous instructions stores the result of the previous operation in internal DPU registers fixes the value of Input3 with Mbf8 and stores the result in internal registers implements the operation OR between the results obtained with the previous instructions
CON crisp1 multiplies the result of the last operation with the crisp value crisp1
Example 2, the priority of the operator is fixed by the brackets:
IF (Input3 IS Mbf1 AND Input4 IS NOT Mbf15) OR (Input1 IS Mbf6 OR Input6 IS NOT Mbf14) THEN Crisp2
LDP 3 1 LDN 4 15 FZAND SKM LDP 1 6 LDN 2 14 FZOR LDK LDM FZOR fixes the value of Input3 with Mbf1 and stores the result in internal registers calculates the NOT value of Input4 with Mbf15 and stores the result in internal registers implements the operation AND between the results obtained with the previous instructions stores the result of the previous operation in register M fixes the value of Input1 with Mbf6 and stores the result in internal registers calculates the NOT value of Input6 with Mbf14 and stores the result in internal registers implements the operation OR between the results obtained with the previous instructions stores the result of the previous operation in internal DPU registers copies the value of the register M in internal DPU registers implements the operation OR between the last two values stored in DPU registers
CON crisp2 multiplies the result of the last operation with the crisp value crisp2 At the end of the fuzzy rule, by using the instruction OUT RAM_reg, a byte is written. Afterwards, the control of the algorithm returns to the CU.
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8 A/D CONVERTER 8.1 Introduction The A/D Converter of ST52X430 is an 8-bit analog to digital converter with up to 8 analog inputs offering 8 bit resolution with a total accuracy of 1 LSB and a typical conversion time of 8.2 s with a 20 MHz clock. This period also includes the 5.1 s of the integral Sample and Hold circuitry, which minimizes the need for external components and allows quick sampling of the signal for a minimum warping effect and Integral conversion error. Conversion is performed in 82 A/D clock pulses. The A/D clock is derived from the clock master. The maximum A/D clock frequency has to be 10 MHz. When the master clock is higher than 10 MHz it has to be divided by 2 using the SCK bit of the A/D configuration register REG_CONF 3 (See Table 8.1). The A/D peripheral converts the input voltage with a process of successive approximations using a fixed clock frequency derived from the oscillator. The conversion range is between the analog VSS and VDD references. The converter uses a fully differential analog input configuration for the best noise immunity and Figure 8.1 A/D Converter Structure precision performance, along with one separate supply (VDDA), allowing the best supply noise rejection. Up to 8 multiplexed Analog Inputs are available. A group of signals can be converted sequentially by simply programming the starting address of the last analog channel to be converted. Single or continuous conversion mode are available. The result of the conversion is stored in an 8-bit Input Register (from IR 1 to IR 8). The A/D converter is controlled via the Configuration Register REG_CONF 3. A Power-Down programmable bit allows the A/D converter to be set to a minimum consumption idle status. The ST52X430 Interrupt Unit provides one maskable channel for the End of Conversion (EOC). 8.2 Operational Description The conversion is monotonic, meaning that the result never decreases if the analog input doesn't and never increases if the analog input doesn't. If input voltage is greater than or equal to Vdda (Voltage Reference high) then the result is equal to FFh (full scale) without an overflow indication.
CONFIGURATION REGISTER 3 INPUT REGISTER
STR LP POW SEQ SCK CH0 CH1 CH2
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A/D CHANNEL 0 A/D CHANNEL 1 A/D CHANNEL 2 A/D CHANNEL 3 A/D CHANNEL 4 A/D CHANNEL 5 A/D CHANNEL 6 A/D CHANNEL 7
PB0/AIN0 CONTROL LOGIC SAMPLE & HOLD ANALOG MUX PB1/AIN1 PB2/AIN2 PB3/AIN3 PB4/AIN4 PB5/AIN5 SUCCESSIVE APPROXMATION A/D CONVERTER PB6/AIN6 PB7/PA7/AIN7
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If input voltage is less than VSS (voltage reference low) then the result is equal to 00h. The A/D converter is linear and the digital result of the conversion is provided by the following formula: 255inputVoltageDigitalresult = ----------------------------------------------referenceVoltage Where Reference Voltage is Vdda - Vss. The accuracy of the conversion is described in the Electrical Characteristics Section. The A/D converter is not affected by the WAIT mode. When the MCU enters HALT mode with A/D converter enabled, the converter is disabled until HALT mode is terminated and the start-up delay has elapsed. A stabilization period is also required before accurate conversions can be performed. Figure 8.2 Conf. Register (REG_CONF 3) 8.2.1 Operating Modes. Four main operating modes can be selected by setting the values of the LP and SEQ bit in the A/D configuration Register. One Channel Single Mode In this mode (SEQ = `0'', LP = `0') the A/D provides an EOC signal after the end of channel i-th conversion; then the A/D waits for a new start event. Channel i-th is identified by the bit CH0, CH1, CH2. i.e CH(2:0) = `011' means conversion of channel 3 then stop. Multiple Channels Single Mode In this mode (SEQ = `1', LP = `0') the A/D provides an EOC signal after the end of the channels sequence conversion identified by the bit CH0, CH1, CH2; then the A/D waits for a new start event. i.e. CH(2:0) = `011' means conversion of channels 0,1,2 and 3 then stop.
REG_CONF 3 D7 D0 CH2 CH1 CH0 SCK SEQ POW LP STR START/STOP CONVERSION MODE SEL. ON/OFF A/D CONVERSION MODE SEL. CLOCK SELECTOR CHANNELS SEL.
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One Channel Continuous Mode In this mode (SEQ = `0'', LP = `1') a continuous conversion flow is entered by a starting event on the channel selected by the CH0, CH1, CH2 bits For example: CH(2:0) = `011' means continuous conversion of channel 3. At the end of each conversion the relative IR is updated with the last conversion result, while the former value is lost. To stop the conversion STR has to be set to `0'. Multiple Channels Continuous Mode In this mode (SEQ = `1'', LP = `1') a continuous conversion flow is entered by a starting event on the channels selected by the CH0, CH1, CH2 bits. i.e CH(2:0) = `011' means continuous conversion of channel 0,1,2 and 3. At the end of each conversion the relative IRs are updated with the last conversion results, while the former values are lost. To stop the conversion STR has to be set to `0'. 8.2.2 Power Down Mode. Before enabling any A/D operation mode, set the POW bit of the A/D configuration register to `1' at least 60 s before the first conversion starts to enable the biasing circuit inside the analog section of the converter. Clearing the POW bit (POW = `0') is useful when the A/D is not used, reducing the total chip power consumption. This state is also the reset configuration and it is forced by hardware when the core is in HALT state (after a HALT instruction execution). 8.3 A/D Registers Description The result of the conversions of the 8 available channels are loaded in the 8 Input Register from decimal address 1 to decimal address 8. (IR (1:8) see Table 2.2)). Every IR(1:8) is reloaded with a new value at the end of the conversion of the correspondent analog input. By using the assembler instruction: LDRI RAM_Reg. IR_i the value stored in the i-th IR is transferred on the RAM location RAM_Reg. The A/D configuration register is the REG_CONF 3. Figure 6.2 illustrates the structure of this register, which manages the A/D logic operation. The A/D configuration register (REG_CONF 3) is programmable as following: b7-b5 = CH2, CH1, CH0: Last Conversion Address. These 3 bits define the last analog input. The first analog input is converted, then the address is incremented for the successive conversion until the channel identified by CH0CH2 is converted. The (CH2, CH1, CH0) bits define the group of channels to be scanned. When setting CH2=0 CH1=0 CH0=0 only channel 0 is converted. b4 = SCK: Master clock divider. ST52X430 can work with a clock frequency up to 20 MHz. The SCK must be set to `1' when the ST52X430 clock is higher then 10 MHz. It is useful to set SCK = `1' even when the clock master is lower than 10 MHz and a high accuracy is required. b3 = SEQ: Multiple/Single channel. When SEQ is set to `0' the channel identified by CH(2:0) is converted. If SEQ is set to `1' the group of channels identified by CH(2:0) are converted. b2= POW: Power Up/ Power Down. A logical `1' enables the A/D logic and analog circuitry. Logical level `0' disables all power consuming logic, allowing a low power idle status. b1 = LP: Continuous/Single. When this bit is set to `1' (continuous mode), the first conversion sequences are started by the STR bit then a continuous conversion flow is processed. When LP='0' (single mode) only one sequence of conversions is started when STR is set. b0 = STR: Start/Stop. A logical level `1' enables starting a conversion sequence; a logical level `0' stops the conversion. When the A/D is running in the Single Modes (LP='0'), this bit is hardware reset at the end of a conversion sequence. Table 8.1 A/D Conf. Register (Reg_Conf 3)
Bit 0 Name STR Value 0 1 1 LP 0 1 2 POW 0 1 3 SEQ 0 1 4 SCK 0 1 000 5 001 010 6 CH(2:0) 011 100 101 7 110 111 Description Stop Conversion Start Conversion Single Conversion Continuous A/D OFF A/D ON Single Channel Conv. Multiple Channels Conv Clock not Divided Clock Divided Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 47/88
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9 WATCHDOG TIMER 9.1 Operational Description The Watchdog Timer (WDT) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which cause the application program to abandon its normal sequence. The WDT circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the WDT before the end of the programmed time delay. 16 different delays can be selected by using the WDT configuration register. After the end of the delay programmed by the configuration register if the WDT is activated (by using the assembler instruction WDTSFR), it starts a reset cycle pulling the reset pin low. Once the WDT has been activated the application program has to refresh this peripheral (by the WDTSFR instruction) at regular intervals during normal operation in order to prevent an MCU reset. In order to stop the WDT during user program execution the instruction WDTSLP has to be used. The working frequency of the WDT (PRES CLK in the Figure 9.1) is equal to the clock master. The clock master is divided by 500, obtaining the WDT CLK signal, which is used to fix the timeout of the WDT. Table 9.1 Watchdog Timing range (CLK=5 MHz)
WDT timeout period (ms) min max 0.1 937.5
According to the WDT configuration register values, a WDT delay may be defined between 0.1 ms and 937.5 mS when the clock master is 5 MHz. By changing the clock master frequency the timeout delay can be calculated according to the configuration register values REG_CONF 2, as described in the following section.
Warning: changing the REG_CONF2 value when the WDT is active, a WDT reset is generated and the CPU is restarted. To avoid this side effect, use the WDTSLP instruction before changing the REG_CONF2.
Figure 9.1 Watchdog Block Diagram
REG_CONF 2
D3 D2 D1 D0
WDTRFR RESET PRES CLK = CLK MASTER
WDT PRESCALER
WTD CLK
RESET GENERATOR
RESET
WDTSLP
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9.2 Register Description The WDT timeout is defined by setting the value of the REG_CONF 2. The first 4 bits of this register are used, obtaining 16 different delays as illustrated in Table 9.2. In Table 9.2 timeout is expressed by using the number of WDT CLK. The WDT CLK is derived from the clock master by a division factor of 500. Timeout is obtained by multiplying the WDT CLK pulse length for the number of pulses defined by the configuration register REG_CONF 2. Table 9.4 illustrates the pulse lengths for typical values of the clock master. Table 9.3 illustrates the timeout WDT values when the Master Clock is 5 MHz. Table 9.2 WDT REG_CONF 2
2 Bit Name Value 0000 0 0001 0010 0011 0100 1 0101 0110 D(3:0) 0111 1000 2 1001 1010 1011 1100 3 1101 1110 1111 4-7 NC x Timeout Values (WDT 1 625 1250 1875 2500 3125 3750 4375 5000 5625 6250 6875 7500 8125 8750 9375 Not Used 4 5 8 10 20 8 10 16 20 40 0.125 0.1 0.0625 0.05 0.025 4-7 NC 3
Table 9.3 Timeout Values with CLK = 5 MHz
Bit Name Value 0000 0 0001 0010 0011 0100 1 D (3:0) 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 x Timeout Values (ms) 0.1 62.5 125 187.5 250 312.5 375 437.5 500 562.5 625 687.5 750 812.5 875 937.5 Not Used
Reset Configuration `0000'
Table 9.4 Typical WDT CLK Pulse Length
MASTER CLK (MHz) WDT CLK (KHz) WDT CLK PULSE LENGTH (ms)
Reset Configuration `0000'
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10 PWM/TIMER ST52X430 offers three on-chip PWM/Timer peripherals:TIMER0, TIMER1 and TIMER2. The ST52X430 timers have the same internal structure. The timer consists of an 8-bit counter with a 16-bit programmable prescaler, giving a maximum count of 224 (see Figure 10.1). Note: In order to use T0RST, T0STR, T0CLK external signals the related pins must be configured in Input Mode by setting REG_CONF4 and REG_CONF7 registers (see Table 6.4 and Table 10.3) For each timer, the content of the 8-bit counter is incremented on the Rising Edge of the 16-bit prescaler output (PRESCOUT) and it can be read at any instant of the counting phase, saved in a location of RAM memory. The PWM/Timer x Counter value can be read from the Input Register
Figure 10.1 Timer Peripheral Block Diagram
16-BIT PRESCALER CLKM BIT 0 BIT 1 BIT 2 BIT3 BIT 4 BIT5 BIT 14 BIT15
17 - 1 M TIPLEXER UL
PRESCx
TMRCLK TxRES 8-BITCOUNTER BIT 0 BIT 1 BIT 2 BIT3 BIT 4 BIT5 BIT 6 BIT 7
TxSTRT
Next, the generic timer is called Timer x, where x can be 0, 1 or 2. Each timer has two different working modes, which can be selected by setting the correspondent TxMODE bits of REG_CONF5, REG_CONF8 and REG_CONF10 registers: Timer Mode and PWM (Pulse Width Modulation) Mode. All Timers have Autoreload Functions in PWM Mode. Each timer output is available, with its complementary signal on external pins by setting PAx and PCx bits of REG_CONF12 and REG_CONF16 (see Table 10.8 and Table 10.9). Note: In order to enable timer output (TxOUT or TxOUT) the related pin must be configured in Output Mode by setting REG_CONF4 and REG_CONF15 registers (see Table 6.4 and Table 6.6) In particular, TIMER0 can also use external START/STOP signals (Input capture and Output compare), external RESET signal and external CLOCK: PA4/T0STRT, PA0/T0RES and PA5/ T0CLK pins.
PWM_x_COUNT (Input Registers 12, 14 or 16. See Table 2.2). The PWM/Timer x Status can be read from the Input Register PWM_x_STATUS (Input Registers 13, 15 or 17. See Table 2.2 and Table 10.10). 10.1 Timer Mode Timer Mode is selected by fixing the TxMODE bit of REG_CONF5, REG_CONF8 and REG_CONF10 equal to 0 (see Table 10.1, Table 10.4 and Table 10.6). Each TIMERx requires three signals: Timer Clock (TMRCLKx), Timer Reset (TxRES) and Timer Start (TxSTRT) (see Figure 10.1). Each of these signals can be generated internally, or, only for Timer 0, externally by setting T0RST, T0STR, T0CLK bits of REG_CONF7 register. TMRCLKx is the Prescaler x output, which increments the Counter x value on the rising edge. TMRCLKx is obtained from the internal clock signal (CLKM) or, only for TIMER0, from the external signal provided on the PA5/T0CLK pin.
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Figure 10.2 Timer 0 External START/STOP Mode
start
start stop
Level
start stop
start
Edge
Reset
Clock Counted Value
0
1
2
3
4
4
1
0
the
1
TIMER x is
NOTE: The external clock signal applied on the T0CLK pin must have a frequency at least two times smaller than the internal master clock. The prescaler output can be selected by setting the PRESCx bit of REG_CONF6, REG_CONF9 and REG_CONF11 registers (see Table 10.2, Table 10.5 and Table 10.7). TxRES resets the content of the 8-bit counter x to zero. It is generated by the TIRSTx and TxMSK bits of REG_CONF5, REG_CONF7, REG_CONF8 and REG_CONF10 registers (see Table 10.1, Table 10.3, Table 10.4 and Table 10.6). TxSTRT signal starts/stops Timer x counting only if the peripherals are configured in Timer mode. This signal is forced by setting the correspondent TISTRx bit of REG_CONF5, REG_CONF8 and REG_CONF10 registers (see Table 10.1, Table 10.4 and Table 10.6). TxMSK bits mask the reset of each timer and can be utilized to synchronize a simultaneous start of the timers by means (for example), of the following procedure, which starts three timers: 1) TIRST0 = TIRST1 = TIRST2 = 0, 2) TISTR0 = TISTR1 = TISTR2 = 0, 3) T0MSK = T1MSK = T2MSK = 1, 4) TIRST0 = TIRST1 = TIRST2 = 1, 5) TISTR0 = TISTR1 = TISTR2 = 1, 6) T0MSK = T1MSK = T2MSK = 0,
When TxMSK is reset.htfgdhtdfhfd
Figure 10.3 TIMEROUT Signal Type
Prescout*Counter
Timer Output Type 1
Type 2
TIMER 0 START/STOP can be provided externally on the T0STRT pin. In this case, the T0STRT signal allows the user to work in two different modes by setting the TESTR configuration bit of REG_CONF5 register (see Figure 10.2) (Input capture): LEVEL (Time Counter): If the T0STRT signal is high the Timer starts counting. When T0STRT is low the counting ceases and the current value is stored in the PWM_0_COUNT Input Register.
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Figure 10.4 PWM Mode with Auto Reload
255 compare value
reload register 0
t
PWM Output Ton T
t
EDGE(Period Counter): After reset, on the first T0STRT rising edge, TIMER 0 starts counting and at the next rising edge it stops. In this manner, the period of an external signal may be measured. Timer x output signal, TIMERxOUT is a signal with a frequency equal to the 16 bit-Prescaler x output signal, TMRCLKx, divided by the Output Register PWM_x_COUNT value (8 bit) (Output Registers 3, 5 or 7. See Table 2.4), which is the value to count. There can be two types of TIMERxOUT waveform: type 1: TIMERxOUT waveform equal to a square wave with a 50% duty-cycle. type 2: TIMERxOUT waveform equal to a pulse signal with the pulse duration equal to the Prescaler x output signal. For each Timer x, the TIMERxOUT waveform type can be selected by setting the correspondent TMRWx bit of REG_CONF6, REG_CONF9 and REG_CONF11 registers (see Table 10.2, Table 10.5 and Table 10.7)
10.2 PWM Mode For each timer, PWM working mode is obtained by setting the correspondent TxMODE bits of REG_CONF5, REG_CONF8 and REG_CONF10 registers to 1 (see Table 10.1, Table 10.4 and Table 10.6). TIMERxOUT, in PWM Mode consists of a signal with a fixed period, whose duty cycle can be modified by the user. The TIMERxOUT signal can be available on the TxOUT pin and the TIMERxOUT inverted signal can be available on the TxOUT pin by setting the PxSL bits of REG_CONF12 and REG_CONF16 (see Table 10.8 and Table 10.9) The PWM TIMERxOUT period can be determined by setting the 16-bit prescaler x output and an initial autoreload 8-bit counter value stored in the Output Register PWM_x_RELOAD, as illustrated in Figure 10.4. NOTE: the Start/Stop and Set/Reset signals should be moved together in PWM mode. If the Start/Stop bit is reset during the PWM mode working, the TxOUT signal keeps its status until the next start.
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The Output Register PWM_x_RELOAD value is automatically reloaded when Counter x restarts counting. The 16-bit Prescaler x divides the master clock, CLKM, or, only for TIMER0, the external T0CLK signal, by the 16-bit Prescaler x. NOTE: The external clock signal, applied on T0CLK pin must have a frequency at least two times smaller than the internal master clock. The Prescaler x output can be selected by setting PRESCx bit of REG_CONF6, REG_CONF9 and REG_CONF11 registers (see Table 10.2, Table 10.5 and Table 10.7). When Counter x reaches the Peripheral Register PWM_x_COUNT value (Compare Value), TIMERxOUT signal changes from high to low level, up to the next counter start. The period of the PWM signal is obtained by using the following equation: T = (255 - PWM _x_RELOAD)x TMR CLKx where TMRCLKx is the output of the 16-bit prescaler x. The duty cycle of the PWM signal is controlled by the Output Register PWM_x_COUNT: Ton =(PWM_x_COUNT- PWM_x_RELOAD)* TMRCLKx If the Output Register PWM_x_COUNT value is 255 the TIMERxOUT signal is always at a high level. If the Output Register PWM_x_COUNT is 0, or less than the PWM_x_RELOAD value, TIMERxOUT signal is always at a low level. NOTE. If PWM_x_RELOAD value increases the duty cycle resolution decreases. By using a 20 MHz clock master a PWM frequency in the range 1.2 Hz to 78.43 Khz can be obtained. NOTE: loading new values of the counter in the PWM_x_COUNT register, in order to avoid side effects, the PWM/Timer counter is updated only at the end of the counting cycle. WARNING: loading new values of the reload in the PWM_x_RELOAD registers, the PWM/Timer is immediately set on-fly. This can cause some side effects during the current counting cycle. The next cycles work normally. This occurs both in Timer and in PWM mode. When the Timers are in Reset, or when the device is reset, TxOut pins go in threestate. If these outputs are used to drive external devices it is recommended to put a pull-up or a pull-down resistor. 10.3 Timer Interrupt TIMERx can be programmed to generate an Interrupt request until the end of the count or when there is an external TSTART signal. The Timer can generate programmable Interrupts into 4 different modes: Interrupt mode 1: Interrupt on counter Stop. Interrupt mode 2: Interrupt on Rising Edge of TIMEROUT. Interrupt mode 3: Interrupt on Falling Edge of TIMEROUT. Interrupt mode 4: Interrupt on both edges of TIMEROUT. Interrupt mode can be selected by means of INTSLx and INTEx bits of the REG_CONF5, REG_CONF8 and REG_CONF10 registers (see Table 10.1, Table 10.4 and Table 10.6). NOTE: the interrupt on TIMEROUT rising edge is also generated after the Start. WARNING: the first interrupt after starting PWM is not generated if the counter value is 0, 255, or lower than the reload value. If the PWM/ Timer is configured with the Interrupt on Stop and the Start/Stop is configured as external, a low signal in the STRT pin determines a PWM/ Timer interrupt even if the peripheral is off. If the interrupt is configured on falling edge, a reset signal generates an interrupt request.
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Table 10.1 Configuration Register 5 Description
Bit 0 TIRST0 1 0 1 TERST 1 0 2 TISTR0 1 0 3 TESTR 1 00 4 INTE0 5 11 0 6 INTSL0 1 0 7 T0MODE 1 PWM MODE - not used TIMER0 Interrupt on Counter Stop TIMER0 Interrupt on TIMER0OUT TIMER MODE 01 10 External START on Edge TIMER0 Interrupt on TIMER Interrupt on TIMEROUT Falling Edge TIMER0 Interrupt on TIMER0OUT Rising Edge TIMER0 Interrupt on Both Edges of TIMER0OUT PWM/TIMER 0 Internal START External START on Level External RESET on Edge PWM/TIMER 0 Internal STOP PWM/TIMER 0 Internal SET External RESET on Level Name Value 0 Description PWM/TIMER 0 Internal RESET
Figure 10.5 Configuration Register 5
REG_CONF 5 TIMER 0 D7 D6 D5 D4 D3 D2 D1 D0
TIRST0: Timer 0 Internal RESET TERST: Timer 0 External RESET on Edge/Level TISTR0: Timer 0 Internal START TESTR: Timer 0 External START on Edge/Level INTE0: Timer 0 Interrupt on TIMER0OUT Rising/Falling Edge INTSL0: Timer 0 Interrupt Source selection T0MODE: Timer 0 working mode
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Table 10.2 Configuration Register 6 Description
Bit Name Value 00000 0 00001 00010 00011 00100 1 00101 00110 00111 2 PRESC0 01000 01001 01010 3 01011 01100 01101 01110 4 01111 10000 0 5 TMRW0 1 6 7 TIMER0OUT Waveform equal to square wave - not used - not used TIMER0 Clock=CLKM/32768 TIMER0 Clock=CLKM /65536 TIMER0OUT Waveform equal to pulse wave Description TIMER0 Clock = CLKM / 1 TIMER0 Clock = CLKM / 2 TIMER0 Clock = CLKM / 4 TIMER0 Clock = CLKM / 8 TIMER0 Clock = CLKM / 16 TIMER0 Clock = CLKM / 32 TIMER0 Clock = CLKM / 64 TIMER0 Clock = CLKM / 128 TIMER0 Clock = CLKM / 256 TIMER0 Clock = CLKM / 512 TIMER0 Clock = CLKM/1024 TIMER0 Clock = CLKM/2048 TIMER0 Clock = CLKM/4096 TIMER0 Clock = CLKM/8192 TIMER0 Clock=CLKM/16384
Figure 10.6 Configuration Register 6
REG_CONF 6 TIMER 0 D7 D6 D5 D4 D3 D2 D1 D0
PRESC0: Timer 0 Prescaler TMRW0: TIMER0OUT waveform not used
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Table 10.3 Configuration Register 7 Description
Bit 0 T0RST 1 Name Value 00 01 10 11 2 T0STR 3 00 01 10 11 4 T0CLK 0 1 5 T0MSK 0 1 6 T2MSK 0 1 7 T1MSK 0 1 Description TIMER0 RESET Internal TIMER0 RESET External TIMER0 RESET External or Internal - not used TIMER0 START Internal TIMER0 START External TIMER0 START External or Internal - not used TIMER0 Clock Internal TIMER0 Clock External TIMER 0 reset synchronization mask. TIMER0 reset synchronization mask. TIMER2 reset synchronization mask. TIMER2 reset synchronization mask. TIMER1 reset synchronization mask. TIMER1 reset synchronization mask.
Figure 10.7 Configuration Register 7
REG_CONF 7
TIMER 0, TIMER 1, TIMER2 D7 D6 D5 D4 D3 D2 D1 D0
T0RST: Tim er 0 RESET Mode T0STR: Tim er 0 START Mode T0CLK: T0MSK: T2MSK: T1MSK: Tim er 0 Tim er 0 Tim er 2 Tim er 1 Clock Source RESET Mask RESET Mask RESET Mask
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Table 10.4 Config. Register 8 Description
Bit 0 Name TIRST1 1 1 0 2 TISTR1 1 3 00 4 INTE1 5 01 10 11 0 6 INTSL1 1 0 7 T1MODE 1 PWM MODE TIMER1 Interrupt on TIMER1OUT Rising Edge TIMER1 Interrupt on Both Edges of TIMER1OUT - not used TIMER1 Interrupt on Counter Stop TIMER1 Interrupt on TIMER1OUT TIMER MODE PWM/TIMER 1 Internal START - not used TIMER1 Interrupt on TIMER1OUT Falling Edge PWM/TIMER 1 Internal SET - not used PWM/TIMER 1 Internal STOP Value 0 Description PWM/TIMER 1 Internal RESET
Figure 10.8 Configuration Register 8
REG_CONF 8 TIMER 1 D7 D6 D5 D4 D3 D2 D1 D0
TIRST1: Timer 1 RESET - not used TISTR1: Timer 1 START - not used INTE1: Timer 1 Interrupt on TIMER1OUT Rising/Falling Edge INTSL1: Timer 1 Interrupt Source selection T1MODE: Timer 1 working mode
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Table 10.5 Config. Register 9 Description
Bit Name Value 00000 0 00001 00010 00011 00100 1 00101 00110 00111 2 PRESC1 01000 01001 01010 3 01011 01100 01101 4 01110 01111 10000 5 6 7 TMRW1 0 1 Description TIMER1 Clock = CLKM / 1 TIMER1 Clock = CLKM / 2 TIMER1 Clock = CLKM / 4 TIMER1 Clock = CLKM / 8 TIMER1 Clock = CLKM / 16 TIMER1 Clock = CLKM / 32 TIMER1 Clock = CLKM / 64 TIMER1 Clock = CLKM / 128 TIMER1 Clock = CLKM / 256 TIMER1 Clock = CLKM / 512 TIMER1 Clock =CLKM / 1024 TIMER1 Clock =CLKM / 2048 TIMER1 Clock =CLKM / 4096 TIMER1 Clock =CLKM / 8192 TIMER1 Clock =CLKM/16384 TIMER1 Clock=CLKM /32768 TIMER1 Clock=CLKM /65536 TIMER1OUT Waveform equal to pulse wave TIMER1OUT Waveform equal to square wave - not used - not used
Figure 10.9 Configuration Register 9
REG_CONF 9 TIMER 1 D7 D6 D5 D4 D3 D2 D1 D0
PRESC1: Timer 1 Prescaler TMRW1: TIMER1OUT waveform not used
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Table 10.6 Config. Register 10 Description
Bit Name Value 0 0 TIRST2 1 1 0 2 TISTR2 1 3 00 4 INTE2 01 10 5 11 0 6 INTSL2 1 0 7 T2MODE 1 PWM MODE - not used TIMER2 Interrupt on Counter Stop TIMER2 Interrupt on TIMER2OUT TIMER MODE TIMER2 Interrupt on TIMER2OUT Rising Edge TIMER2 Interrupt on Both Edges of TIMER2OUT PWM/TIMER 2 Internal START - not used TIMER2 Interrupt on TIMER2OUT Falling Edge PWM/TIMER 2 Internal SET - not used PWM/TIMER 2 Internal STOP Description PWM/TIMER 2 Internal RESET
Figure 10.10 Configuration Register 10
REG_CONF 10 TIMER 2 D7 D6 D5 D4 D3 D2 D1 D0
TIRST2: Timer 2 RESET - not used TISTR2: Timer 2 START - not used INTE2: Timer 2 Interrupt on TIMER2OUT Rising/Falling Edge INTSL2: Timer 2 Interrupt Source selection T2MODE: Timer 2 working mode
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Table 10.7 Config. Register 11 Description
Bit Name Value 00000 0 00001 00010 00011 1 00100 00101 00110 00111 2 PRESC2 01000 01001 01010 3 01011 01100 01101 4 01110 01111 10000 5 6 7 TMRW2 0 1 Description TIMER2 Clock = CLKM / 1 TIMER2 Clock = CLKM / 2 TIMER2 Clock = CLKM / 4 TIMER2 Clock = CLKM / 8 TIMER2 Clock = CLKM / 16 TIMER2 Clock = CLKM / 32 TIMER2 Clock = CLKM / 64 TIMER2 Clock = CLKM / 128 TIMER2 Clock = CLKM / 256 TIMER2 Clock = CLKM / 512 TIMER2 Clock = CLKM /1024 TIMER2 Clock = CLKM/ 2048 TIMER2 Clock = CLKM/ 4096 TIMER2 Clock = CLKM/ 8192 TIMER2 Clock= CLKM/16384 TIMER2 Clock =CLKM/32768 TIMER2 Clock =CLKM/65536 TIMER2OUT Waveform equal to pulse wave TIMER2OUT Waveform equal to square wave - not used - not used
Figure 10.11 Configuration register 11
REG_CONF 11 TIMER 2 D7 D6 D5 D4 D3 D2 D1 D0
PRESC2: Timer 2 Prescaler TMRW2: TIMER2OUT waveform not used
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Table 10.8 Config. Register 12 Description
Bit 0 Name PA1 Value 0 1 1 PA2 0 1 2 PA3 0 1 3 4 5 6 7 PASZ 0 1 Description Pin PA1/T0OUT equal to PORT A Digital I/O Pin PA1/ T0OUT equal to T0OUT Pin PA2/ T1OUT equal to PORT A Digital I/O Pin PA2/ T1OUT equal to T1OUT Pin PA3/ T2OUT equal to PORT A Digital I/O Pin PA3/ T2OUT equal to T2OUT PORT A bits = 7 PORT A bits = 8 - not used - not used - not used - not used
Figure 10.12 Configuration Register 12
REG_CONF 12 DIGITAL PORT D7 D6 D5 D4 D3 D2 D1 D0
PA1: Pin PA1/T0OUT setting PA2: Pin PA2/T1OUT setting PA3: Pin PA3/T2OUT setting PASZ: PORT A size not used
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Table 10.9 Config. Register 16 Description
Bit 0 Name PC1 Value 1 0 1 PC2 1 0 2 PC3 1 0 3 4-7 PC4 1 0 Description Pin T0OUT/PC1 equal to PORT C Digital I/O Pin T0OUT/PC1 equal to T0OUT Pin T1OUT/PC2 equal to PORT C Digital I/O Pin T1OUT/PC2 equal to T1OUT Pin T2OUT/PC3 equal to PORT C Digital I/O Pin T2OUT/PC3 equal to T2OUT Pin Tx/PC4 is configured as Port C Digital I/O Pin Tx/PC4 is configured as SCI output Tx - not used
Figure 10.13 Configuration Register 16
R E G _C O N F 16 D IG IT A L P O R T D7 D6 D5 D4 D3 D2 D1 D0
P C 1 : P in T 0 O U T /P C 1 se tting PC 2: Pin T1 O U T /P C2 se tting PC 3: Pin T2 O U T /P C 3 se tting PC 4: Pin Tx/PC 4 se tting no t used
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Table 10.10 Input Registers 13. PWM_0_STATUS
Bit 0 Name STR0 Value 0 1 1 RST0 0 1 2 3 4 5 6 7 Description TIMER 0 is STOP TIMER 0 START TIMER 0 is RESET TIMER 0 is NOT - not used - not used - not used - not used - not used - not used 2 3 4 5 6 7 1 RST2
Table 10.12 Input Registers 17. PWM_2_STATUS
Bit 0 Name STR2 Value 0 1 0 1 Description TIMER 2 is STOP TIMER 2 is START TIMER 2 is RESET TIMER 2 is NOT - not used - not used - not used - not used - not used - not used
Table 10.11 Input Registers 15. PWM_1_STATUS
Bit 0 Name STR1S Value 0 1 1 RST1S 0 1 2 3 4 5 6 7 Description TIMER 1 is STOP TIMER 1 is START TIMER 1 is RESET TIMER 1 is NOT - not used - not used - not used - not used - not used - not used
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11 SERIAL COMMUNICATION INTERFACE The Serial Communication Interface (SCI) integrated into the ST52X430 fuzzy processor provides a general purpose shift register peripheral, which links several widely distributed MCU's through their SCI subsystem. SCI offers a serial interface providing communication with common baud rates up to 38,400 and flexible character format. SCI is a full-duplex UART-type asynchronous system with standard Non Return to Zero (NRZ) format for the transmitted/received bit. The length of the transmitted word is 10/11 bits (1 start bit, 8/ 9 data bits, 1 stop bit). SCI is composed of three modules: Receiver, Transmitter and Baud-Rate Generator. It is configured by means of Configuration Registers 19 and 20. WARNING: IN ORDER TO WORK PROPERLY WITH SCI PERIPHERALS MAINTAINING THE DESIRED BAUD RATE A SYSTEM CLOCK OF ONLY 5, 10 OR 20 MHz MUST BE USED. 11.1 SCI Receiver block The SCI Receiver block manages the synchronization of the serial data stream and stores data characters. The SCI Receiver is mainly formed by two sub-systems: Recovery Buffer Block and SCDR_RX Block. Figure 11.2 SCI Block Diagram Figure 11.1 SCI transmitted word structures
STOP
DATA
START
10 9
8
7
6
5
4
3
2
1
0
STOP
DATA
START
9
8
7
6
5
4
3
2
1
0
The RE configuration bit (bit 1 of the Configuration Register 20) enables the SCI Receiver when it is set to "1". SCI receives data deriving from the RX/PC5 pin and drives the Recovery Buffer Block, which is a high-speed shift register operating at a clock frequency (CLOCK_RX) that is 16 times higher than the fixed baud rate (CLOCK_TX). This sampling rate, higher than the Baud Rate clock allows the detection of the START condition, Noise error and Frame error.
SCI
SCI Receiver RAM LDRI ram-i 18 IR 18
RECOVERY BUFFER SCDR_RX
RX/PC5
SCI Transmitter RAM / EPROM LDPR 9 ram-i or LDPE 9 epr-i
SHIFT REGISTER
TX/PC4
OR 9
SCDR_TX
MCLK
Baud-Rate Generator
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When the SCI Receiver is in IDLE status, it is waiting for the START condition, which is obtained with a logic level 0, consecutive to a logic level 1. This condition is detected if a logic level 0 is sampled after three logic levels 1 with the fixed sampling time. The recognition of the START bit forces the SCI Receiver Block to enter in a data acquisition sequence. The data acquisition sequence is configured via Configuration Register 20 as follows. The 2 bits, M, of the Configuration Register 20 allows the definition of the serial mode as illustrated in Table 11.1. In the case that M=10, 8 is used to set the parity check in order to perform (as indicated in Table 11.1). Recognition of the STOP condition allows data received from the Recovery Buffer to be transferred to the SCDR_RX buffer, adding the eventual ninth data bit, according to the meaning illustrated in previous Table 11.1. After this operation, the RXF flag of the SCI Status Input Register 19 (Figure 11.3) is set to logic level 1. The Control Unit reads data from the SCDR_RX buffer (in read-only mode) with the LDRI instruction, addressing Input Register 18, and provides a reset at logic level 0 to the RXF flag. If data of the Recovery Buffer is ready to be transferred into the SCDR_RX buffer, but the previous one was not read by the Core yet, an OVERRUN Error takes place: the status flag OVERR indicates the error condition. In this case, the information stored in the SCDR_RX buffer is not altered, but the one that has caused the OVERRUN error can be overwritten by new data deriving from the serial data line. Recovery Buffer Block This block is structured as a synchronized finite state machine on the CLOCK_RX signal. When the Recovery Buffer Block is in IDLE state it waits for the reception of the correct 1 and 0 sequence representing START. The recognition takes place by sampling the input RX/PC5 at CLOCK_RX frequency, which has a frequency that is 16 times higher than CLOCK_TX. While the external transmitter sends a single bit, the Recovery Buffer Block samples 16 states (from SAMPLE1 to SAMPLE16). The analysis of the RX/PC5 input signal is carried out providing three samples for each bit received. If these three samples are not equal, then the noise error flag, NSERR, of Input Register 19 is set to 1 and the data value received will be the one assumed by the majority of the samples. The procedure above allows SCI not to become IDLE, because of a limited noise due to "an erroneous sampling". The transmission is recognized as correct and the noise flag is set. Table 11.1 Configuration Register 20 Setting
Bit Name Value 0 0 TE 1 0 1 RE 1 00 2 M 01 10 3 11 0 4 T8 1 000 5 001 010 011 6 BRSL 100 101 7 110 111 9600 baud 19200 baud 38400 baud Not Used 9, No Parity, 1 bit stop Parity Odd, if Parity is selected (M = 10); otherwise 9th Data bit Parity Even, if Parity is selected (M = 10); otherwise 9th Data bit 600 baud 1200 baud 2400baud 4800 baud 8, No Parity, 2 bit stop 8, Parity, 1 bit stop Receiver ENABLED 8, No Parity, 1 bit stop Transmission ENABLED Receiver DISABLED Description Transmission
At the end of the reception of a bit, Recovery Buffer Block will repeat the same step 9 times: one for the stop acquisition (10 times in case of 9-bit data, double stop or parity check). At the end of data reception the Recovery Buffer Block will supply information on eventual frame errors by setting the FRERR flag bit of Input Register 19 to 1.
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A frame error can occur if the parity check hasn't been successfully achieved or if the STOP bit hasn't been detected. If the Recovery Buffer Block receives 10 consecutive bits at logic level 0, a break error occurs and an interrupt routine request starts. SCDR_RX Block It is a finite state machine synchronized with the clock master signal, CKM. The SCDR_RX block waits for the signal of complete reception from the Recovery Buffer, in order to load the word received. Moreover, the SCDR_RX block loads the values of FRERR and NSERR flag bits (Input Register 19), and sets the RXF flag to 1. Data is transferred to RAM and the RXF flag is reset to 0 by using the LDRI instruction in order to indicate that the SCDR_RX block is empty. If new data arrives before the previous one has been transferred to Register File, an overrun error occurs and OVERR flag of Input Register 19 is set to 1. 11.2 SCI Transmitter Block The SCI Transmitter Block consists of the following blocks: SCDR_TX and SHIFT REGISTER, synchronized, respectively, with the clock master signal (CKM) and the CLOCK_TX. The whole block receives the settings for the following transmission modes (see Table 11.1) through Configuration Register 20 (M bits): s 8-bit word and a single stop signal
s
Table 11.2 Configuration Register 19 Setting
Bit 0 1 ECKF 2 Name Value Description Not used
00 01 10 11 0
5 MHz 10 MHz 20 MHz 5 MHz SCI End Transmission Interrupt Disabled SCI End Transmission Interrupt Enabled SCI Transmission Data Register Empty Interrupt Disabled SCI Transmission Data Register Empty Interrupt Enabled SCI Break Error Interrupt Disabled
3
TXC 1
0 4 TDRE 1
0 5 BRK 1
8-bit word plus a parity bit and a single stop signal 8-bit word plus a double stop signal 9-bit word
6 OVR 1 0
SCI Break Error Interrupt Enabled
s s
SCI Overrun Error Interrupt Disabled
In case of 9 bit frame transmission, the most significative bit arrives through T8 of the Configuration Register 20. Instead, in an 8-bit transmission T8 is used to configure SCI according to information contained in M (see Table 11.1). In particular, it is used to choose the polarity control (even or odds) in order to implement the parity check. After a RESET signal RST, the SCDR_TX block is in IDLE state until it receives the enabling signal TE=1, of Configuration Register 20. Data is loaded on the peripheral register (OR 9) by using the instruction LPPR or LDPE. If TE=1 the data to be transmitted is transferred from DR_TX block and flag of Input Register 19. TXEM is reset to 0 in order to indicate that the SCDR_TX block is full.
SCI Overrun Error Interrupt Enabled SCI Received Data Register Full Interrupt Disabled SCI Received Data Register Full Interrupt Enabled
0 7 RDRF 1
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Figure 11.3 SCI Status Input Register
SCI_ST Input Register 19
D7 D6 D5 D4 D3 D2 D1 D0
TXEND TXEM R8 - END TRANSMISSION - TRANSMISSION DATA REGISTER EMPTY - RECEIVED NINTH BIT
NOT USED OVERR - OVERRUN ERROR RXF FRERR NSERR - RECEIVE DATA REGISTER FULL - FRAME ERROR - NOISE ERROR
If the core supplies new data it can't be loaded in the SCDR_TX block until the current data hasn't been unloaded on the Shift Register block. Therefore, data may be loaded in the SCDR_TX Block only when TXEM is 1. When the SHIFT REGISTER Block loads data to be transmitted on an internal buffer, TXEND is reset to 0 in order to indicate the beginning of a new transmission. At the end of transmission TXEND is set to 1, allowing to load new data coming from SCDR_TX in the SHIFT REGISTER. Note: TXEND = 1 does not mean SCDR_TX is ready to receive new data. For this reason it is better to utilize the TXEM signal in order to synchronize the LDPR instruction to the SCI TRANSMITTER block If the ST52X430 core resets TE to 0, the transmission is interrupted, but the SCI Transmitter block completes the transmission in progress before reset. Warning: after the stop bit in SCI transmission an idle time is present before the next start bit. This time is equal to the duration of a bit transmission. 11.3 Baud Rate Generator Block The Baud Rate Generator Block performs the division of the clock master signal (CKM), in a set of synchronism frequencies for the serial bit reception/transmission on the external line. Table 11.1 illustrates the set of frequencies selected by means of BRSL (Configuration Register 20).
Reception frequency (CLOCK_RX) is 16 times higher than transmission frequency (CLOCK_TX). The following example illustrates a simple way to use SCI to receive and transmit data: LDRC 1 155 LDCR 20 1 These instructions load value 155 on the Configuration Register 20 fixing the Baud Rate=9600, 8 bit data, TE=1, RE=1; Parity; 1 stop bit.
LDRC 1 252 LDCR 19 4 SCI Interrupts enabled, frequency 20 MHz clock
LDRC 1 170 LDPR 9 1 WAITI LDRI 6 19 Save the SCI status register on the RAM Save the received data on a RAM register Send data to transmission buffer
LDRI 1 18
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12 ELECTRICAL CHARACTERISTICS 12.1 Parameter Conditions Unless otherwise specified, all voltages are referred to V ss. 12.1.1 Minimum and Maximum values. Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of environment temperature, supply voltage and frequencies production testing on 100% of the devices with an environmental temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data is based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. The minimum and maximum values are based on characterization and refer to sample tests, representing the mean value plus or minus three times the standard deviation (mean 3). 12.1.2 Typical values. Unless otherwise specified, typical data is based on TA=25C, VDD=5V (for the 4.5VDD5.5V voltage range). They are provided only as design guidelines and are not tested. 12.1.3 Typical curves. Unless otherwise specified, all typical curves are provided only as design guidelines and are not tested. Figure 12.1 Pin loading conditions 12.2 Absolute Maximum Ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 12.1.4 Loading capacitor. The loading condition used for pin parameter measurement is illustrated in Figure 12.1. 12.1.5 Pin input voltage. Input voltage measurement on a pin of the device is described in Figure 12.2
Figure 12.2 Pin input Voltage
ST52 PIN
VIN
ST52 PIN
CL
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Table 12.1 Voltage Characteristics
Symbol VDD-VSS VDDA-V SSA |VDDA|and |VSSA| |VSSA-VSSX| VIN VDESD Ratings Supply voltage Analog reference voltage(VDDV DDA) Variation between different digital power pins Variation between digital and analog ground pins Input voltage on Vpp Input voltage on any other pin 1) & 2) Electro-static discharge voltage Maximum Value 6.5 6.5 50 50 VSS-0.3 to 13 VSS-0.3 to VDD+0.3 2000 V mV Unit V
Table 12.2 Current Characteristics
Symbol IVDD IVSS IIO Ratings Total current in VDD power lines (source)3) Total current in VSS ground lines (sink)3) Output current sunk by any standard I/O and control pin Output current source by any I/Os and control pin Injected current on VPP pin Injected current on RESET pin IINJ(PIN) Injected current on OSCin and OSCout pins Injected current on any other pin 4)
IINJ(PIN)
Maximum Value 100 100 25 -25 5 5 5
5 20
Unit
mA
Total Injected current (sum of all I/O and control pins) 4)
Table 12.3 Thermal Characteristics
Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature Maximum Value -65 to +150 150 Unit C C
Notes: 1. Connecting RESET and I/O Pins directly to VDD or VSS could damage the device if the unintentional internal reset is generated or an unexpected change of I/O configuration occurs (for example, due to the corrupted program counter). In order to guarantee safe operation, this connection has to be performed via a pull-up or pull-down resistor (typical: 4.7k for RESET, 10K for I/Os). Unused I/O pins must be tied in the same manner to VDD or VSS according to their reset configuration. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to I INJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VINVDD while a negative injection is induced by VIN69/88
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12.3 Recommended Operating Condition Operating condition: VDD=5V10%; TA=0/125C (unless otherwise specified). Table 12.4 Recommended Operating Conditions
Symbol VDD 2) VPP VO VDDA, VSSA fOSC 1)2) Parameter Operating Supply Programming Voltage Output Voltage Analog Supply Voltage Analog Ground Oscillator Frequency Test Condition Refer to Figure 12.3 Min. 3.5 11.4 VSS VDD-0.3 VSS-0.3 2 VDD VSS 12 Typ. Max 5.5 12.6 VDD VDD+0.3 VSS+0.3 20 MHz V Unit
Notes: 1. It is reccomendend to insert a capacitor beetwen VDD and VSS for improving noise rejection. Reccomended values are 10 F (electrolytic or tantalum) and/or 100 nF (ceramic). 2. In order to use SCI correctly maintaining the programmed baud rates, fosc must be set to 5, 10 or 20 Mhz. 3. A lower VDD decreasing fosc (see Figure 12.3). Data illustrated in the figure are characterized but not tested.
Figure 12.3 fosc Maximum Operating Frequency versus VDD supply
20 18 16
fosc. max (MHz)
14 12 10 8 6 4 2 Functionality not guarateed in this area 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Functionality guarateed in this area Functionality not guarateed in this area
Vdd (V)
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12.4 Supply Current Characteristics Supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. Table 12.5 Supply Current in RUN and WAIT Mode
Symbol Parameter Conditions fosc=2 Mhz fosc=4 Mhz Supply current in RUN mode 1) VDD=5V5% IDD fosc=5 Mhz, fosc=10 fosc=20 fosc=2 MHz fosc=4 MHz Supply current in WAIT mode2) fosc=5 MHz fosc=10 fosc=20 Typ 4.0 7.5 9.0 17.5 33.5 2.0 4.0 5.0 10.0 18.5 Max3) 6.0 10.0 12.0 20.0 37.0 3.0 5.0 6.0 12.0 22.0 mA Unit
The test condition in RUN mode for all the IDD measurements are: OSCin = external square wave, from rail to rail; OSCout = floating; All I/O pins tristated pulled to VDD TA=90C
TA=90C
Notes: 1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals switched off; clock input (OSCin driven by external square wave). 2. CPU in WAIT mode with all I/O pins in input mode with a static value at V DD or VSS (no load), all peripherals switched off; clock input (OSCin driven by external square wave). 3. Data based on characterization results, tested in production at VDDmax and foscmax.
Figure 12.4 Typical IDD in RUN vs fosc
Figure 12.5 Typical IDD in WAIT vs fosc
35 30
20 18 16
25 IDD [mA] 20 15 10 5
14 IDD [mA] 12 10 8 6 4 2
0 3.5 3.7 3.9 4.1 4.3 4.5 VDD [V] 2M Hz 4M Hz 5M Hz 10 M Hz 20 M Hz 4.7 4.9 5.1 5.3 5.5
0 3.5 3.7 3.9 4.1 4.3 4.5 VDD [V] 2 MHz 4 MHz 5 MHz 10 MHz 20 MHz 4.7 4.9 5.1 5.3 5.5
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Table 12.6 Supply Current in HALT Mode
Symbol IDDA Parameter Supply current in HALT mode2) Conditions 3.0 V VDD 5.5 V Typ1) 1 Max 10 Unit A
Notes: 1. Typical data is based on TA = 25 C 2. All I/O pins in input mode with a static value at VDD or VSS (no load)
Table 12.7 On-Chip Peripheral Symbol
IDDA
Parameter
ADC Supply current when converting
Conditions
fosc=20MHz, VDDA = 5 5% V, VssA = Vss VSSA=VSS
Typ3
1
Max4
2
Unit
mA
Notes: 3. Typical data is based on TA=25C, VDDA=5 V. 4. Data is based on characterization results and isn't tested in production.
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12.5 Clock and Timing Characteristics Operating Conditions: VDD=5V 5%, TA=0/125C, unless otherwise specified
Table 12.8 General Timing Parameters
Symbol fosc tCLH tCLL tSET tHLD tWRESET tWINT tIR tIF tOR tOF Parameters Oscillator Frequency Clock High Clock Low Setup Hold Minimum Reset Pulse Minimum External Input Rise Time Input Fall Time Output Rise Time Output Fall See Fig. 11.6 See Fig. 11.6 fosc =20MHz fosc =20MHz See Fig. 11.7 See Fig. 11.7 CLOAD=10pF CLOAD=10pF 10 10 100 nS 100 15 15 Test Condition Min 1 25 25 5 5 Typ. Max 20 250 250 Unit MH
Figure 12.6 Data Input Timing
Figure 12.7 I/O Rise and Fall Timing
tCLL tCLH
50%
tCP
Data
50%
tSET
Clock
tHLD
50%
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12.6 Memory Characteristics Subject to general operating conditions for VDD, fosc and TA, unless otherwise specified. Table 12.9 RAM and Registers
Symbol VRM Parameter Data retention mode1) Conditions HALT mode (or RESET) Min. 1.6 Typ. Max Unit V
Table 12.10 EPROM Program Memory
Symbol Parameter Conditions Lamp wavelength 2537 A UV lamp is placed 1 inch from the device window without any interposed filters TA =+55C Min. Typ. Max Unit Watt, sec/cm2)
WERASE
UV lamp
15
tERASE
Erase time2)
15
20
min.
tRET
Data Retention
20
years
Notes: 1. Minimum VDD supply voltage without losing data stored into RAM (in HALT mode or under RESET) or into hardware registers (only in HALT mode). Guaranteed by construction, not tested in production. 2. Data is provided only as a guideline.
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12.7 ESD Pin Protection Strategy In order to protect an integrated circuit against Electro-Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. Stress generally affects the circuit elements, which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. The elements that are to be protected must not receive excessive current, voltage, or heating within their structure. An ESD network combines the different input and output protections. This network works by allowing safe discharge paths for the pins subject to ESD stress. Two critical ESD stress cases are presented in Figure 12.8 and Figure 12.9 for standard pins. 12.7.1 Standard Pin Protection In order to protect the output structure the following elements are added: - A diode to VDD (3a) and a diode from VSS (3b) - A protection device between VDD and VSS (4) In order protect the input structure the following elements are added: - A resistor in series with pad (1) - A diode to VDD (2a) and a diode from VSS (2b) - A protection device between VDD and VSS (4)
Figure 12.8 Safe discharge path subjected to ESD stress
VD D
(3 a) (2 a)
VDD
O UT M ain path P ath to avoid
(3 b)
(4 )
IN
(1 )
(2 b)
VS S
V SS
Figure 12.9 Negative Stress on a Standard Pad vs. VDD
VDD
(3a) (2a)
VDD
OUT Main path
(3b)
(4)
IN
(1)
(2b)
VSS
VSS
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12.7.2 Multi-supply Configuration. When several types of ground (VSS, VSSA,...) and power supply (VDD, VDDA,...) are available for any reason (better noise immunity...), the structure illustrated in Figure 12.10 is implemented in order to protect the device against ESD.
Figure 12.10 ESD Protection for Multisupply Configuration
VDD
VDDA
(4)
VDDA
VSS
(4)
VSSA
BACK TO BACK DIODE BETW EEN GROUNDS
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12.8 Port Pin Characteristics 12.8.1 General Characteristics. Subject to general operating condition for VDD, fosc, and TA , unless otherwise specified.
Symbol
Parameter
Condition
Min
Typ1)
Max
Unit
CMOS type low level input voltage. Port B pins. (See Fig 11.13) VIL TTL type Schmitt trigger low level input voltage. Port A and Port C pins. (See Fig. 11.12) CMOS type high level input voltage. Port B pins. (See Fig 11.13) VIH TTL type Schmitt trigger high level input voltage. Port A and Port C pins. (See Fig. 11.12) Vhys Schmitt trigger voltage hysteresis 2) 2.2 3.3
1.5
0.8
V
1
IL
Input leakage current
VSSVINV DD
1 A
IS
Static current consumption3)
Floating input mode
200
Notes: 1. Unless otherwise specified, typical data is based on TA=25 C and VDD=5 V 2. Hysteresis voltage between Schmitt trigger switching level. Based on characterization results, not tested in production. 3. Configuration is not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure 12.11. Data based on design simulation and/or technology characteristics is not tested in production. Figure 12.11 Recommended configuration for unused pins
VDD
10k
ST52
UNUSED I/O PORT 10k
UNUSED I/O PORT
ST52
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ST52T430/E430
Subject to general operating conditions for VDD, fosc, and TA, unless otherwise specified. Table 12.11 Output Voltage Levels
Symbol Parameter Conditions Min Typ Max VSS+ 0.4 V VOH2) Notes: 1. The IIO current sunk must always respects the absolute maximum rating specified in Section 12.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS 2. The IIO sourced current must always respect the absolute maximum rating specified in Section 12.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Output high level voltage for standard I/ O pin when 8 pins are sourced at same time. VDD=5V, IIO=- 8mA VDD0.5 Unit
VOL1)
Output low level voltage for standard I/O pin when 8 pins are sunk at same time.
VDD=5V, IIO=+8mA
Figure 12.12 TTL-Level input Schmitt Trigger
Figure 12.13 Port B pins CMOS-level input
5
5
4 V (V) o 3
V = 5V DD TA = 25C (TYPICAL)
V (V) o
4
VDD= 5V
3
TA = 25C (TYPICAL)
2
2
1
1
0
0.5 0.8 1.0
1.5 V (V) i
2.0 2.5
0
2.0 Vi (V)
3.3
5.0
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ST52T430/E430
Subject to general operating condition for VDD, fosc, and TA, unless otherwise specified. Table 12.12 Output Driving Current
Symbol Parameter Test Conditions Min Typ Max Unit
RS
Input protection resistor
All input Pins
1
k
CS
Pin Capacitance
All input Pins
5
pF
Figure 12.14 Port A and Port C pin Equivalent Circuit
VDD
Device Input/Output CS
RS
VIN
VOUT VSS VSS
Figure 12.15 Port B Pin Equivalent Circuit
VDD
Device Input/Output CS
RS
VIN
VOUT VSS VSS
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ST52T430/E430
12.9 Control Pin Characteristics 12.9.1 RESET pin. Subject to general operating conditions for VDD, fosc, and TA, unless otherwise specified Table 12.13 Reset pin
Symbol Parameter Conditions Min Typ Max Unit
VIL
Input low level voltage1)
VDD= 5 V
1.8
VIH
Input high level voltage1)
VDD= 5 V
2.8
V
Vhys
Schmitt trigger voltage hysteresis2)
VDD= 5 V
0.8
tw(RSTL)out
General reset pulse duration
30 S
th(RSTL)int
External reset pulse hold time
20
12.9.2 VPP pin. Subject to general operating conditions for V DD, fosc, and TA,unless otherwise specified. Table 12.14 V PP4) pin
Symbol VIL VIH Parameter Input low level voltage3) Input high level voltage3) Conditions Min VSS VDD-0.1 Typ Max 0.2 V 12.6 Unit
Notes: 1. Data is based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching level. Based on characterization results not tested in production. 3. Data is based on design simulation and/or technology characteristics, not tested in production. 4. In working mode VPP must be tied to VSS
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12.10 8-bit A/D Characteristics Subject to general operating conditions for VDD, fosc, and TA, unless otherwise specified.
Symbol Res A TOT tC
VAN
Parameter Resolution Total Accuracy1) Conversion Time Conversion Range Zero Scale Voltage Full Scale Voltage Analog Input Current during Conversion Analog Input Capacitance ADC Clock frequency
Conditions
Min
Typ 8
Max
Unit bit LSB
S
1 MHz1 82/fADC VSSA VDDA VSSA VDDA
V V V A
VZI VFS
Conversion result = 00 Hex Conversion result = FF Hex fADC=20MHz
ADI ACIN fADC
0.1 25 fosc/2 fosc
pF MHz
Notes:
1. Noise on VDDA, VSSA < 40 mV
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ST52T430/E430
Table 12.15 SS034 PACKAGE MECHANICAL DATA
DIM MIN A A1 B C D E e H h k l 10.16 0.635 0 0.6096 2.4638 0.127 0.3556 0.23114 17.7292 7.4168 1.016 10.414 0.7366 8 1.016 0.400 0.025 0 0.024 mm TYP. MAX 2.6416 0.2921 0.4826 0.3175 18.0594 7.5946 MIN 0.097 0.005 0.014 0.0091 0.698 0.292 0.040 0.410 0.029 8 0.040 inch. TYP. MAX 0.104 0.0115 0.019 0.0125 0.711 0.299
h L
h A
K
e
34
18
E
A1
B
1
17
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H
C
ST52T430/E430
Table 12.16 PDIP32 Shrink PACKAGE MECHANICAL DATA
DIM MIN A A1 A2 b b1 C D E E1 e eAl eB eC L 0.100 0.120 mm TYP. MAX MIN 0.140 0.02 0.120 0.014 0.030 0.008 1.080 0.390 0.300 0.140 0.018 0.040 0.010 1.100 0.410 0.350 0.070 0.400 0.500 0.055 0.150 0.18 0.023 0.055 0.014 1.120 0.435 0.370 inch TYP. 0.148 MAX 0.200
A2
E
A
eC
L
b1
b e D
A1
E1 C eA eB
32
17
1
16
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ST52T430/E430
Table 12.17 CSDIP32W Shrink PACKAGE MECHANICAL DATA
DIM MIN A A1 B B1 C D D1 E1 e G G1 G2 L Q 0.170 mm TYP. MAX MIN 0.097 0.025 0.016 0.035 0.008 1.168 1.042 0.382 0.065 0.010 1.180 1.050 0.390 0.070 0.375 0.580 0.044 0.175 0.180 0.290 0.012 1.192 1.058 0.398 0.075 inch. TYP. 0.115 0.035 0.018 MAX 0.133 0.045 0.020
E1
G2
G1
G1
A1
L
A
B
e
C
Q
B1 D1 D
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ST52T430/E430
Table 12.18 TQFP32 PACKAGE MECHANICAL DATA
DIM MIN A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09 9.00 7.00 5.60 0.80 9.00 7.00 5.60 0.60 1.00 0(min.), 7(max.) 0.75 0.018 1.40 0.37 mm TYP. MAX 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 0.354 0.276 0.220 0.031 0.354 0.276 0.220 0.024 0.039 0.030 0.055 0.015 MIN inch. TYP. MAX 0.063 0.006 0.057 0.018 0.008
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ST52T430/E430
ORDERING INFORMATION Each device is available for production in user programmable version (OTP) as well as in factory programmed version (FASTROM). OTP devices are shipped to the customer with a default blank content FFh, while FASTROM factory programmed parts contain the code sent by the customer. There is one common EPROM version for debugging and prototyping, which features the maximum memory size and peripherals of the family. Care must be taken only to use resources available on the target device. Figure 12.16 Device Types Selection Guide
ST52 t nnn c m p y
TEMPERATURE RANGE: 6 = -40 to 85 C PACKAGES: B = PDIP M = PSO T = TQFP MEMORY SIZE: 1 = 2 Kb 2 = 4 Kb 3 = 8 Kb PIN COUNT: K = 32/34 pin SUBFAMILY: 430 MEMORY TYPE: T = OTP E = EPROM FAMILY
PART NUMBER ST52T430K1M6 ST52T430K2M6 ST52T430K3M6 ST52T430K1B6 ST52T430K2B6 ST52T430K3B6 ST52T430K1T6 ST52T430K2T6 ST52T430K3T6 ST52E430K3D6 ST52X430/KIT
TEMPERATURE RANGE -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
PACKAGE SSO34 SSO34 SSO34 PSDIP32 PSDIP32 PSDIP32 TQFP32 TQFP32 TQFP32 CSDIP32W DEVELOPMENT KIT
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ST52T430/E430
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Full Product Information at http://mcu.st.com Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Canada - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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